AD629(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD629 Datasheet PDF : 12 Pages
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5V/DIV
+10V
VOUT
0V
OUTPUT
ERROR
1mV = 0.01%
5V/DIV
0V
VOUT
–10V
OUTPUT
ERROR
AD629
1mV = 0.01%
1mV/DIV
10s/DIV
Figure 23. Settling Time to 0.01%, For 0 V to 10 V Output
Step; G = –1, RL = 2 kΩ
1mV/DIV
10s/DIV
Figure 26. Settling Time to 0.01% for 0 V to –10 V Output
Step; G = –1, RL = 2 kΩ
350
N = 2180
300
n Ϸ 200 PCS. FROM
10 ASSEMBLY LOTS
250
200
150
100
50
0
–150
–100
–50
0
50
100
150
COMMON-MODE REJECTION RATIO – ppm
Figure 24. Typical Distribution of Common-Mode
Rejection; Package Option N-8
300
N = 2180
250
n Ϸ 200 PCS. FROM
10 ASSEMBLY LOTS
200
150
100
50
0
–900 –600 –300
0
300
600
900
OFFSET VOLTAGE – V
Figure 27. Typical Distribution of Offset Voltage;
Package Option N-8
400
350
N = 2180
n Ϸ 200 PCS. FROM
10 ASSEMBLY LOTS
300
250
200
150
100
50
0
–600
–400
–200
0
200
–1 GAIN ERROR – ppm
400
600
Figure 25. Typical Distribution of –1 Gain Error;
Package Option N-8
400
350
N = 2180
n Ϸ 200 PCS. FROM
10 ASSEMBLY LOTS
300
250
200
150
100
50
0
–600
–400
–200
0
200
400
600
+1 GAIN ERROR – ppm
Figure 28. Typical Distribution of +1 Gain Error;
Package Option N-8
REV. A
–7–
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