LTC1707 데이터 시트보기 (PDF) - Linear Technology
부품명
상세내역
제조사
LTC1707 Datasheet PDF : 16 Pages
| |||
LTC1707
APPLICATIO S I FOR ATIO
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • CLOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1707. These items are also illustrated graphically in
the layout diagram of Figure 7. Check the following in your
layout:
1. Are the signal and power grounds segregated? The
LTC1707 signal ground consists of the resistive
divider, the optional compensation network (RC and
CC1), CSS, CREF and CC2. The power ground consists of
the (–) plate of CIN, the (–) plate of COUT and Pin 4 of the
LTC1707. The power ground traces should be kept
short, direct and wide. The signal ground and power
ground should converge to a common node in a star-
ground configuration.
2. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of COUT and signal ground.
3. Does the (+) plate of CIN connect to VIN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node SW away from sensitive small-
signal nodes.
CREF
CC2
OPTIONAL
RC
CC1
1
ITH
8
VREF
CSS
2
7
RUN/SS SYNC/MODE
LTC1707
R2
3
6
VFB
VIN
R1
4
GND
SW 5
L1
+
+
CIN
BOLD LINES INDICATE HIGH CURRENT PATHS
+
VOUT VIN
COUT
––
1707 F07
Figure 7. LTC1707 Layout Diagram
11
Share Link: 