ST24LC21B1TR 데이터 시트보기 (PDF) - STMicroelectronics
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ST24LC21B1TR Datasheet PDF : 18 Pages
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ST24LC21
Table 7. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 400kHz
(TA = 0 to 70 °C; VCC = 2.5V to 5.5V)
Symbol
tCH1CH2 (1)
tCL1CL2 (1)
tDH1DH2 (1)
tDL1DL2 (1)
tCHDX (2)
Alt
tR
tF
tR
tF
tSU:STA
Parameter
Clock Rise Time
Clock Fall Time
SDA Rise Time
SDA Fall Time
Clock High to Input Transition
Min
Max
300
300
20
300
20
300
600
tCHCL
tHIGH
Clock Pulse Width High
600
tDLCL
tHD:STA
Input Low to Clock Low (START)
600
tCLDX
tHD:DAT
Clock Low to Input Transition
0
tCLCH
tLOW
Clock Pulse Width Low
1.3
tDXCX
tSU:DAT
Input Transition to Clock Transition
100
tCHDH
tSU:STO Clock High to Input High (STOP)
600
tDHDL
tBUF
Input High to Input Low (Bus Free)
1.3
tCLQV
tAA
Clock Low to Data Out Valid
200
900
tCLQX
tDH
Clock Low to Data Out Transition
200
fC
fSCL
Clock Frequency
400
tW
tWR
Write Time
10
Notes: 1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
Unit
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
kHz
ms
Data Input. During data input the ST24LC21 sam-
ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation
the SDA signal must be stable during the clock low
to high transition and the data must change ONLY
when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24LC21, the
master must initiate a START condition. Following
this, the master sends onto the SDA bus line 8 bits
(MSB first) corresponding to the device select code
(7 bits) and a READ or WRITE bit. The 4 most
significant bits of the device select code are the
device type identifier, corresponding to the I2C bus
definition. For these memories the 4 bits are fixed
as 1010b. The following 3 bits are Don’t Care. The
8th bit sent is the read or write bit (RW), this bit is
set to ’1’ for read and ’0’ for write operations. If a
match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
Write Operations
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. After receipt of the byte address the de-
vice again responds with an acknowledge.
In I2C bidirectional mode, any write command with
VCLK = 0 will not modify data and will be acknow-
ledged on data bytes, as shown in Figure 11.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition.
Page Write. The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 8 bytes of data, which are each acknow-
ledged by the memory.
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