MAX3875 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3875

2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC

Maxim Integrated 

2.5Gbps, Low-Power, +3.3V

Clock Recovery and Data Retiming IC

Input and Output Terminations

The MAX3875’s digital outputs (SDO+, SDO-, SCLKO+,

SCLKO-) are designed to interface with PECL signal

levels. It is important to bias these ports appropriately.

A circuit that provides a Thevenin equivalent of 50Ω to

VCC - 2V can be used with fixed impedance transmis-

sion lines for proper termination. To ensure best perfor-

mance, the differential outputs must have balanced

loads. The input termination can be driven differentially,

or can be driven single-ended by externally biasing

SDI- or SLBI- to the center of the voltage swing.

Jitter Tolerance and Input

Sensitivity Trade-Offs

When the received data amplitude is higher than

50mVp-p, the MAX3875 provides a typical jitter toler-

ance of 0.45UI at jitter frequencies greater than 10MHz.

The SDH/SONET jitter tolerance specification is 0.15UI,

leaving a jitter allowance of 0.3UI for receiver preampli-

fier and postamplifier design.

The BER is better than 1 · 10-10 for input signals greater

than 10mVp-p. At 10mVp-p, jitter tolerance will be

degraded, but will still be above the SDH/SONET

requirement. The user can make a trade-off between jit-

ter tolerance and input sensitivity according to the spe-

cific application. Refer to the Typical Operating

Characteristics for Jitter Tolerance and BER vs. Input

Amplitude graphs.

Applications Information

Consecutive Identical Digits (CID)

The MAX3875 has a low phase and frequency drift in

the absence of data transitions. As a result, long runs of

consecutive zeros and ones can be tolerated while

maintaining a BER of 1 · 10-10. The CID tolerance is

tested using a 213 - 1 PRBS, substituting a long run of

zeros to simulate the worst case. A CID tolerance of

2000 bits is typical.

Phase Adjust

The internal clock is aligned to the center of the data

eye. For specific applications this sampling position

can be shifted using the PHADJ inputs to optimize BER

performance. The PHADJ inputs operate with differen-

tial input voltages up to ±1.5V. A simple resistor-divider

with a bypass capacitor is sufficient to set these levels.

When the PHADJ inputs are not used, they should be

tied directly to VCC.

System Loopback

The MAX3875 is designed to allow system loopback

testing. The user can connect a serializer output in a

transceiver directly to the SLBI+ and SLBI- inputs of the

MAX3875 for system diagnostics. To select the SLBI±

inputs, apply a TTL logic high to the SIS pin.

PECL Input Levels

When interfacing with differential PECL input levels, it is

important to attenuate the signal while still maintaining

50Ω termination (Figure 6). AC coupling is also

required to maintain the input common-mode level.

Layout

The MAX3875’s performance can be significantly

affected by circuit board layout and design. Use good

high-frequency design techniques, including minimiz-

ing ground inductance and using fixed-impedance

transmission lines on the data and clock signals.

Power-supply decoupling should be placed as close to

VCC as possible. Take care to isolate the input from the

output signals to reduce feedthrough.

VCC

0.1µF 25Ω

SDI+

PECL

LEVELS

0.1µF

100Ω

25Ω

SDI-

50Ω 50Ω

MAX3875

Figure 6. PECL Input Interface

____________________________________________________________________________________ 12-97

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