AD1879 데이터 시트보기 (PDF) - Analog Devices

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AD1879

High Performance 16-/18-Bit ΣΔ Stereo ADCs

Analog Devices 

AD1878/AD1879

32 1 2 3

BCK I/O

14 15 16 17 18 19 20

31 32 1 2 3

14 15 16 17 18 19 20

31 32 1

WCK INPUT

LRCK I/O

PREVIOUS DATA

AD1878 LSB

DATA OUTPUT

ZEROS

LEFT DATA

MSB MSB–1 MSB–2 MSB–3

LSB–1 LSB

ZEROS

RIGHT DATA

MSB MSB–1 MSB–2 MSB–3

LSB–1 LSB

Figure 10. AD1878 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 16th BCK

(Master Mode or Slave Mode)

32 1 2 3

BCK I/O

WCK INPUT

14 15 16 17 18 19 20

31 32 1 2 3

14 15 16 17 18 19 20

31 32 1

LRCK I/O

PREVIOUS DATA

AD1879

DATA OUTPUT

LSB

ZEROS

LEFT DATA

MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

LSB–1 LSB

ZEROS

RIGHT DATA

MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

LSB–1 LSB

Figure 11. AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 14th BCK

(Master Mode or Slave Mode)

32 1 2 3

BCK I/O

WCK INPUT

16 17 18 19 20 21 22

LRCK I/O

31 32 1 2 3

16 17 18 19 20 21 22

31 32 1

AD1879

DATA OUTPUT

AD1878

DATA OUTPUT

LEFT DATA

ZEROS MSB MSB–1 LSB–3 LSB-2 LSB–1 LSB

LEFT DATA

ZEROS MSB MSB–1 LSB–1 LSB

ZEROS

ZEROS

RIGHT DATA

ZEROS MSB MSB–1 LSB–3 LSB-2 LSB–1 LSB

RIGHT DATA

ZEROS MSB MSB–1 LSB–1 LSB

ZEROS

ZEROS

Figure 12. AD1878/AD1879 64-Bit Output Frame Timing with WCK as Input: WCK Hl During 1st BCK

(Master Mode or Slave Mode)

16 1 2 3 4 5 6

BCK I/O

15 16 1 2 3 4 5 6

15 16 1

LRCK I/O

AD1879

DATA OUTPUT

AD1878

DATA OUTPUT

LEFT DATA

MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

LEFT DATA

MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

RIGHT DATA

LSB–3 LSB–2 MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

RIGHT DATA

LSB-1 LSB MSB MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

LSB–3 LSB–2

LSB-1 LSB

Figure 13. AD1878/AD1879 32-Bit Output Frame Timing (Master Mode or Slave Mode)

At the other limit, if the word clock (WCK) is HI during the first

bit clock (BCK) of the field, then the MSB of the output word

will be valid on the rising edge of the 2nd bit clock (BCK) as

shown in Figure 12. The effect is to delay the MSB for one bit

clock cycle into the field, making the output data compatible at

the data format level with the I2S data format.

In 64-bit frame modes with word clock (WCK) as an input, the

relative placement of the word clock (WCK) input can vary

from 32-bit field to 32-bit field, even within the same 64-bit

frame. For example, within a single 64-bit frame the left word

could be right-justified (by keeping WCK LO) and the right

word could be in an I2S-compatible data format (by having

WCK HI at the beginning of the second field).

REV. 0

–11–

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