AD1879 데이터 시트보기 (PDF) - Analog Devices
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AD1879 Datasheet PDF : 16 Pages
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AD1878/AD1879
249kΩ
RIGHT INPUT
5.62kΩ
5.62kΩ
5.62kΩ
100kΩ
.1µF 5.62kΩ
VSS
NE5532 OR OP-275
249kΩ
VCC .1µF 249kΩ
5.62kΩ
LEFT
INPUT
5.62kΩ
5.62kΩ
100kΩ
5.62kΩ
249kΩ
100pF
5.76kΩ
NE5532 OR
VCC .1µF
OP-275
.01µF
51Ω
NPO
10µF
200Ω
.1µF
VSS
51Ω
.0047 µF
NPO
14
REFR
AD1878/79
5.49kΩ
.01µF
NPO
12
VINR–
100pF
13
VINR+
16
VINL+
100pF
5.36kΩ
.01µF
NPO
17
VINL–
51Ω
VCC
.1µF
.0047 µF
NPO
51Ω
REFL
15
200Ω
.1µF
VSS
.01µF
NPO
5.90kΩ
100pF
NE5532 OR
OP-275
10µF
Figure 2. AD1878/AD1879 Recommended Input Structure
VCC
AGND
VSS
VDD
DGND
0.1µF
0.1µF
7805
IN
OUT
22µF
GND
22µF GND
IN
OUT
7905
+5V ANALOG
0.1µF
10µF
0.1µF 10µF
+5V DIGITAL
–5V
ANALOG
0.1µF
22µF
+12V < VCC < +18V
–12V > VSS > – 18V
Figure 3. AD1878/AD1879 Recommended Power Condi-
tioning Circuit (If ±5 V Supplies Are Not Already Available)
The trim potentiometers shown in Figure 2 connecting the
minus (–) inputs of the driving op amps permit trimming out dc
offset, if desired.
Note that the driving op amp feedback resistors are all slightly
different values. These values produce a slight differential gain
imbalance and were derived empirically to minimize second
harmonic distortion on average and produce the best overall
THD without part-by-part trimming. Replacing one of these
feedback resistors in each channel with a trim potentiometer
allows trimming the differential gain imbalance for part-by-part
optimal performance. We have done this in the lab by parallel-
ing 100 kΩ trim potentiometers around the 5.49 kΩ and
5.36 kΩ input feedback resistors for the VIN plus (+) signals
that can be found in Figure 2. By trimming gain imbalance, sec-
ond harmonic distortion can always be eliminated. In “Specifi-
cations,” a distinction is drawn between trimmed and untrimmed
signal-to (noise + distortion) and trimmed and untrimmed total
harmonic distortion. The untrimmed specifications are tested to
the input structure shown in Figure 2. The trimmed specifica-
tions are based on a part-by-part trim of this differential gain to
eliminate the second harmonic.
The input circuit of Figure 2 could be implemented with a
single pair of operational amplifiers per channel, one inverting
and one noninverting. The recommended architecture shown in
Figure 2 using three inverting op amps per channel provides iso-
lation of the op amp inputs from charge dumped back from the
AD1878/AD1879’s input capacitors when these large capacitors
switch. The performance from a two op amp per channel input
structure is not quite as good as the structure recommended,
but it is close and may be adequate in many applications.
Layout and Decoupling Considerations
Obtaining the best possible performance from a state-of-the-art
data converter like the AD1878/AD1879 requires close atten-
tion to board layout. From extensive experimentation, we have
discovered principles that produce typical values of 103 dB dy-
namic range and 98 dB S/(THD+N) in your system. Schematics
of our AD1878/AD1879 Evaluation Board, which implements
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below in descend-
ing order of importance. The first two pertain to bypassing and
are illustrated in Figure 4.
10µF
–5V
+5V
ANALOG
ANALOG
10µF
8 21
19
10 18
AVSS1 AVSS1 AVDD1 AGND AGND
+5V DIGITAL
AD1878/ 79
26
CLKIN
OSCILLATOR
0.1µF
AVSS2 AVDD2 DVDD DGND DGND DVDD
9
20 5
6 23
22
10µF
0.1µF
0.1µF
–5V
ANALOG +5V
10µF
ANALOG
+5V
DIGITAL
10µF
+5V
DIGITAL
Figure 4. AD1878/AD1879 Recommended Bypassing and
Oscillator Circuits
• The digital bypassing of the AD1878/AD1879 is the most
critical item on the board layout. There are two pairs of digi-
tal supply pins of the part, each pair on opposite sides (Pins 5
and 6 and Pins 22 and 23). The user should tie a bypass ca-
pacitor set (0.1 µF ceramic and 10 µF tantalum) on EACH
pair of supply pins as close to the pins as possible. The traces
between these package pins and the capacitors should be as
short and as wide as possible. This will prevent digital supply
current transients from being inductively transmitted to the
inputs of the part.
• The analog input bypassing is the second most critical item.
Use 0.01 µF NPO ceramic capacitors from each input pin to
the analog ground plane, with a clear ground path from the
bypass capacitor to the AGND pin on the same side of the
package (Pins 10 and 18). The trace between this package
pin and the capacitor should be as short and as wide as pos-
sible. A 0.0047 µF NPO ceramic capacitor should be placed
–8–
REV. 0
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