KU376 데이터 시트보기 (PDF) - Intel

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KU376

376™ HIGH PERFORMANCE 32-BIT EMBEDDED PROCESSOR

Intel 

376 EMBEDDED PROCESSOR

The following table lists a brief description of each pin on the 80376 The following definitions are used in

these descriptions

The named signal is active LOW

I

Input signal

O Output signal

I O Input and Output signal

No electrical connection

Symbol

CLK2

RESET

D15 – D0

A23 – A1

WR

DC

M IO

LOCK

ADS

NA

READY

BHE BLE

HOLD

Type

I

I

IO

O

O

O

O

O

O

I

I

O

I

Name and Function

CLK2 provides the fundamental timing for the 80376 For additional

information see Clock in Section 4 1

RESET suspends any operation in progress and places the 80376 in a

known reset state See Interrupt Signals in Section 4 1 for additional

information

DATA BUS inputs data during memory I O and interrupt acknowledge

read cycles and outputs data during memory and I O write cycles See

Data Bus in Section 4 1 for additional information

ADDRESS BUS outputs physical memory or port I O addresses See

Address Bus in Section 4 1 for additional information

WRITE READ is a bus cycle definition pin that distinguishes write

cycles from read cycles See Bus Cycle Definition Signals in Section

4 1 for additional information

DATA CONTROL is a bus cycle definition pin that distinguishes data

cycles either memory or I O from control cycles which are interrupt

acknowledge halt and instruction fetching See Bus Cycle Definition

Signals in Section 4 1 for additional information

MEMORY I O is a bus cycle definition pin that distinguishes memory

cycles from input output cycles See Bus Cycle Definition Signals in

Section 4 1 for additional information

BUS LOCK is a bus cycle definition pin that indicates that other

system bus masters are denied access to the system bus while it is

active See Bus Cycle Definition Signals in Section 4 1 for additional

information

ADDRESS STATUS indicates that a valid bus cycle definition and

address (W R D C M IO BHE BLE and A23 – A1) are being driven at

the 80376 pins See Bus Control Signals in Section 4 1 for additional

information

NEXT ADDRESS is used to request address pipelining See Bus

Control Signals in Section 4 1 for additional information

BUS READY terminates the bus cycle See Bus Control Signals in

Section 4 1 for additional information

BYTE ENABLES indicate which data bytes of the data bus take part in

a bus cycle See Address Bus in Section 4 1 for additional

information

BUS HOLD REQUEST input allows another bus master to request

control of the local bus See Bus Arbitration Signals in Section 4 1

for additional information

5

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