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ACTS240DTR 데이터 시트보기 (PDF) - Intersil

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ACTS240DTR Datasheet PDF : 3 Pages
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Die Characteristics
DIE DIMENSIONS:
(2540µm x 2540µm x 533µm ±51µm)
100 x 100 x 21mils ±2mil
METALLIZATION:
Type: Al Si Cu
Thickness: 10.0kÅ ±2kÅ
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire)
Bond Pad #20 (VCC) First
Bond Pad #10 (Gnd) Uses Two Bond Wires
Bond Pad #20 (VCC) Uses Two Bond Wires
Metallization Mask Layout
AI1 AEN
(2) (1)
ACTS240T
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (SiO2)
Thickness: 8.0kÅ ±1.0kÅ
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm2
TRANSISTOR COUNT:
164
PROCESS:
CMOS SOS
ACTS240T
VCC VCC
(20) (20)
BEN
(19)
BO4 (3)
AI2 (4)
BO3 (5)
AI3 (6)
BO2 (7)
AI4 (8)
BO1 (9)
(10) (10)
GND GND
(18) AO1
(17) BI4
(16) AO2
(15) BI3
(14) AO3
(13) BI2
AO4 (12)
(11)
BI1
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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