MAX726 데이터 시트보기 (PDF) - Maxim Integrated

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MAX726

5A/2A Step-Down, PWM, Switch-Mode DC-DC Regulators

Maxim Integrated 

5A/2A Step-Down, PWM,

Switch-Mode DC-DC Regulators

Be sure that the selected capacitor can handle the ripple

current over the required temperature range. Also locate

the input capacitor very close to the MAX724/MAX726 and

use minimum length leads (surface-mount or radial

through-hole types). In most applications, ESR is more

important than actual capacitance value since electrolytic

capacitors are mostly resistive at the MAX724/MAX726's

100kHz switching frequency.

__________Applications Information

Setting Output Voltage

R1 and R2 set output voltage as follows:

R1 = VOUT R2 -R2

2.21V

2.21V is the reference voltage, so setting R2 to 2.21kΩ

(standard 1% resistor value) results in 1mA flowing

through R1 and R2 and simplifies the above equation.

Other values will also work for R2, but should not

exceed 4kΩ.

Synchronizing the Oscillator

The MAX724/MAX726 can be synchronized to an exter-

nal 110kHz to 160kHz source by pulsing the VC pin to

ground at the desired clock rate. This is conveniently

done with the collector of an external grounded-emitter

NPN transistor. VC should be pulled low for 300ns.

Doing this may have some impact on output regulation,

but the effect should be minimal for compensation

resistor values between 1kΩ and 4kΩ.

Power Dissipation

The MAX724/MAX726 draw about 7.5mA operating cur-

rent, which is largely independent of input voltage or

load current. They draw an additional 5mA during

switch on-time. Power dissipated in the internal VSW

transistor is proportional to load current and depends

on both conduction losses (product of switch on-volt-

age and switch current) and dynamic switching losses

(due to switch rise and fall times). Total MAX724 power

dissipation can be calculated as follows:

P = VIN [7.5mA + 5mA (DC) + 2 IOUT tSW fOSC] + . . .

. . . DC [IOUT (1.8V) + 0.1Ω (IOUT)2]

DC = Duty Cycle = VOUT + 0.5V

VIN - 2V

tSW = Overlap Time = 50ns + (3ns/A) IOUT

where tSW is "overlap" time. Switch dissipation is

momentarily high during overlap time because both cur-

rent and voltage appear across the switch at the same

time. tSW is approximately: [50ns + (3ns/A) (IOUT)] for

the MAX724.

Power dissipation in the MAX726 can be estimated in

exactly the same way as the MAX724, except that 1.1V

(and not 1.8V) is a more reasonable value for the nomi-

nal voltage drop across the on-board power switch.

Ground Connections

GND demands a short low-noise connection to ensure

good load regulation. Since the internal reference is

referred to GND, errors in the GND pin voltage get mul-

tiplied by the error amplifier and appear at the output.

If the MAX724/MAX726 GND pin is separated from the

negative side of the load, then high load return current

can generate significant error across a seemingly small

ground resistance. Single-point grounding is the most

effective way to eliminate these errors. A recommend-

ed ground arrangement is shown in Figure 4.

Overload Protection

The VSW current is internally limited to about 6.5A in the

MAX724 and 2.6A in the MAX726. In addition, another

feature of the MAX724/MAX726's overload protection

scheme is that the oscillator frequency is reduced

when the output voltage falls below approximately half

its regulated value. This is the case during short-circuit

and heavy overload conditions.

Since the minimum on-time for the switch is about

0.6µs, frequency reduction during overload ensures

that switch duty cycle can fall to a low enough value to

maintain control of output current. At the normal

100kHz switching frequency, an on-time as short as

R1

MAX724

MAX726 FB

GND

HIGH CURRENT

RETURN PATH

R2

NEGATIVE OUTPUT

NODE WHERE LOAD

REGULATION WILL

BE MEASURED

Figure 4. Recommended Ground Connection

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