PSOT24LC-T7(2003) 데이터 시트보기 (PDF) - Protek Devices
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PSOT24LC-T7 Datasheet PDF : 5 Pages
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APPLICATION NOTE
PSOT03LC
thru
PSOT36LC
The PSOTxxLC Series are low capacitance TVS arrays designed to protect I/O or data lines from the damaging effects of ESD or EFT. This product
series provides unidirectional & bidirectional protection, with a surge capability of 500 Watts PPP per line for an 8/20µs waveform and ESD protection >
40 kilovolts.
BIDIRECTIONAL COMMON-MODE CONFIGRUATION (Figure 1)
Two PSOTxxLC devices, when used in paralell, provide protection in a
common-mode configuration as depicted in Figure 1.
Figure 1 - Common-Mode I/O Port Protection
I/O LINE
Circuit connectivity is as follows:
✔ I/O Line is connected to Device 1, Pin 1.
✔ I/O Line is connect to Device 2, Pin 2.
✔ Device 1, Pin 2 is connected to ground.
✔ Device 2, Pin 1 is connected to ground.
✔ Device 1 & 2, Pin 3 is not connected.
BIDIRECTIONAL DIFFERENTIAL-MODE CONFIGRUATION (Figure
1)
In addition, two PSOTxxLC devices, when used in paralell, provide
protection in a differential-mode configuration for Ethernet applications as
depicted in Figure 2.
Circuit connectivity is as follows:
1
2
33
2
1
GND
✔ I/O Line 1 is connected to Device 1, Pin 1.
✔ I/O Line 1 is connect to Device 2, Pin 2.
✔ I/O Line 2 is connected to Device 1, Pin 1.
✔ I/O Line 2 is connect to Device 2, Pin 2.
✔ Device 1 & 2, Pin 3 is not connected.
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
I/O 1
Figure 2 - Differential-Mode Ethernet Protection
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following
guidelines are recommended:
✔ The protection device should be placed near the
input terminals or connectors, the device will
divert the transient current immediately before it
can be coupled into the nearby traces.
1
2
33
2
1
I/O 2
✔ The path length between the TVS device and the
protected line should be minimized.
✔ All conductive loops including power and ground
loops should be minimized.
✔ The transient current return path to ground
should be kept as short as possible to reduce
parasitic inductance.
✔ Ground planes should be used whenever
possible. For multilayer PCBs, use ground vias.
05066.R4 8/03
4
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