ML6622 데이터 시트보기 (PDF) - Micro Linear Corporation
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ML6622 Datasheet PDF : 6 Pages
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ML6622
PIN DESCRIPTION
PIN# NAME
1 ENABLE
2 LINKLED
3
VCC
4 ECL OUT+
5 ECL OUT–
6 GND
7 LINK+
8 LINK –
9
VREF
FUNCTION
ECL input active low. When this input
is tied to LINKLED the ECL comparator
output is automatically enabled and
disabled by the Link Detect circuit.
This input can be tied to GND for
continuous enable. When the ECL
Comparator is disabled, ECL OUT–
goes low and ECL OUT+ goes high.
Link Detect Status output. LINKLED is
an open collector active low signal. It
will be active low when the input
signal applied to VIN+,VIN– exceeds
the programmed threshold level at the
THIN pin. Capable of driving a 20mA
LED indicator.
Positive Power Supply. +5 volts
Positive and Negative ECL Comparator
outputs. 1mA internal pull downs are
incorporated.
Ground connection. Used for less
noise sensitive nodes.
Positive ECL Link Detect output. Active
high when the input signal exceeds the
programmed Link Detect threshold.
1mA internal pull down current
sources.
Negative ECL Link Detect output.
Active low when the input signal
exceeds the programmed Link Detect
threshold. 1mA internal pull down
current sources.
A 2.5V reference with respect to GND.
NAME PIN #
10 THIN
11 GNDA
12 VIN–
13 VIN+
14 VCCA
15 CAP
16 CTIMER
FUNCTION
Threshold Input. A voltage applied to
this input pin sets the minimum
amplitude of the input signal required
to cause the link detect to activate. In
most cases this can be tied to VREF.
Ground connection for noise sensitive
circuits in the chip; the input amplifier,
DC restoration loop, part of the
Comparator and part of the link detect
circuit. In some system designs, it may
be advantageous to separate GND and
GNDA.
This input pin should be capacitively
coupled to the input source or to VCCA.
This input pin should be capacitively
coupled to the input source or to VCCA.
Positive power supply VCC for noise
sensitive circuits as mentioned in
GNDA. +5 volts.
A capacitor is tied from this pin to
VREF. This capacitor sets the lower
frequency rejection and helps remove
internal DC offset. This capacitor
should be 10 times larger than the
input capacitors.
A capacitor from this pin to ground
determines the Link Detect response
time. To Meet FDDI specifications this
capacitor should be 2,000pF. This
capacitor can be removed for faster
response time.
PIN CONNECTION
2
ML6622
16-Pin Narrow SOIC (S16N)
ENABLE
LINKLED
VCC
ECL OUT+
ECL OUT–
GND
LINK+
LINK–
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
TOP VIEW
CTIMER
CAP
VCCA
VIN+
VIN–
GNDA
THIN
VREF
Micro Linear
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