M27V320-100M1 데이터 시트보기 (PDF) - STMicroelectronics
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M27V320-100M1 Datasheet PDF : 15 Pages
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M27V320
Figure 10. Programming and Verify Modes AC Waveforms
A0-A20
Q0-Q15
tAVEL
DATA IN
tQVEL
VALID
tEHQX
DATA OUT
tEHAX
tEHQZ
VCC
tVCHEL
tEHVPX
tELQV
GVPP
te Producctt((ss)) E
tVPHEL
tELEH
PROGRAM
tVPLEL
VERIFY
AI02205
sole rodu Note: BYTE = VIH; GVPP High level = 12V.
- Ob te P Figure 11. Programming Flowchart
) le VCC = 6.25V, VPP = 12V
ct(s bso SET MARGIN MODE
rodu ) - O n=0
lete P uct(s NO
so rod ++n
= 25
b P YES
OObsolete FAIL
E = 50µs Pulse
NO
VERIFY
YES
++ Addr
Last NO
Addr
YES
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 100 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 11). During
programing and verify operation a MARGIN
MODE circuit must be activated to guarantee that
each cell is programed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides the necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27V320s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including GVPP of the par-
allel M27V320 may be common. A TTL low level
pulse applied to a M27V320's E input and VPP at
12V, will program that M27V320. A high level E in-
put inhibits the other M27V320s from being pro-
RESET MARGIN MODE
grammed.
Program Verify
CHECK ALL WORDS
BYTE = VIH
1st: VCC = 5V
2nd: VCC = 3V
AI05820
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with
GVPP at VIL. Data should be verified with tELQV af-
ter the falling edge of E.
10/15
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