PEEL22LV10AZ-25 데이터 시트보기 (PDF) - Anachip Corporation

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PEEL22LV10AZ-25

CMOS Programmable Electrically Erasable Logic Device

Anachip Corporation 

A.C. Electrical Characteristics

Over the operating range 9

Switching Waveforms

Inputs, I/O,

Registered Feedback,

Synchronous Preset

Clock

Asynchronous

Reset

Registered

Outputs

Combinatorial

Outputs

Notes:

1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for peri-

ods less than 20 ns.

2. VI and VO are not specified for program/verify operation.

3. The Supply Voltage range of 2.7 to 3.6V was chosen to allow this part to be

used in both 3V ±10% and 3.3V ±10% applications.

4. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90%

levels.

5. I/O pins are 0V and VCC.

6. “Input” refers to an input pin signal.

7. tOE is measured from input transition to VREF±0.1V, TOD is measured from

input transition to VOH-0.1V or VOL+0.1V; VREF=VL.

8. Capacitances are tested on a sample basis.

9. Test conditions assume: signal transition times of 3ns or less from the 10% and

90% points, timing reference levels of 1.5V (Unless otherwise specified).

10. Test one output at a time for a duration of less than 1 second.

11. ICC for a typical application: This parameter is tested with the device pro-

grammed as a 10-bit Counter.

12. Parameters are not 100% tested. Specifications are based on initial character-

ization and are tested after any design process modification that might affect oper-

ational frequency.

13. tPD, tOE, tOD, tCO, tSC, and tAP are approximately 5 ns. slower on the first

transaction from sleep mode.

14. Input at GND.

Anachip Corp.

www.anachip.com.tw

Rev. 1.0 Dec 16, 2004

8/10

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