M68Z128WN 데이터 시트보기 (PDF) - STMicroelectronics

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M68Z128WN

3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable

STMicroelectronics 

M68Z128W

Table 3. Operating Modes

Operation

E1

E2

W

G

DQ0-DQ7

Power

Read

VIL

VIH

VIH

VIH

Hi-Z

Active

Read

VIL

VIH

VIH

VIL

Data Output

Active

Write

VIL

VIH

VIL

X

Data Input

Active

Deselect

VIH

X

X

X

Hi-Z

Standby

Deselect

X

VIL

X

X

Hi-Z

Standby

Note: 1. X = VIH or VIL.

Table 4. AC Measurement Conditions

Input Rise and Fall Times

≤ 15ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages 1.5V

Note: Output Hi-Z is defined as the point where data is no longer

driven.

OPERATIONAL MODE

The M68Z128W has a Chip Enable power down

feature which invokes an automatic standby mode

whenever either Chip Enable is de-asserted (E1 =

High or E2 = Low). An Output Enable (G) signal

provides a high speed tri-state control, allowing

fast read/write cycles to be achieved with the com-

mon I/O data bus. Operational modes are deter-

mined by device control inputs W, E1, and E2 as

summarized in the Operating Modes table.

Figure 3. AC Testing Load Circuit

3.3V

DEVICE

UNDER

TEST

1378Ω

1213Ω

OUT

CL = 50pF or 5pF

CL includes JIG capacitance

AI00697

Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol

Parameter

Test

Condition

Min

CIN

Input Capacitance on all pins (except DQ)

VIN = 0V

COUT (2)

Output Capacitance

VOUT = 0V

Note: 1. Sampled only, not 100% tested.

2. Outputs deselected.

Max

6

8

Unit

pF

pF

3/12

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