AD7822 데이터 시트보기 (PDF) - Analog Devices

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AD7822

3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel Sampling ADCs

Analog Devices 

Figures 2 and 3 below show simplified schematics of the ADC.

When the ADC starts a conversion, the track-and-hold goes into

hold mode and holds the analog input for 120 ns. This is the

acquisition phase as shown in Figure 2, when Switch 2 is in Posi-

tion A. At the point when the track-and-hold returns to its track

mode, this signal is sampled by the sampling capacitor as Switch 2

moves into Position B. The first flash occurs at this instant and

is then followed by the second flash. Typically, the first flash is

complete after 100 ns, i.e., at 220 ns, while the end of the second

flash and hence the 8-bit conversion result is available at 330 ns

(minimum). The maximum conversion time is 420 ns. As shown

in Figure 4, the track-and-hold returns to track mode after 120 ns,

and starts the next acquisition before the end of the current

conversion. Figure 6 shows the ADC transfer function.

REFERENCE

R16

15

D7

R15

D6

SW2

A

VIN T/H 1

14

D5

B SAMPLING

HOLD

CAPACITOR

D4

R14

13

D3

D2

R13

D1

1

D0

R1

TIMING AND

CONTROL

LOGIC

Figure 2. ADC Acquisition Phase

REFERENCE

R16

15

D7

R15

D6

SW2

A

VIN T/H 1

14

D5

B

HOLD

SAMPLING

CAPACITOR

D4

R14

13

D3

D2

R13

D1

1

D0

R1

TIMING AND

CONTROL

LOGIC

Figure 3. ADC Conversion Phase

AD7822/AD7825/AD7829

TRACK

120ns

HOLD

CONVST

t2

t1

EOC

CS

RD

TRACK

HOLD

t3

DB0–DB7

VALID

DATA

Figure 4. Track-and-Hold Timing

TYPICAL CONNECTION DIAGRAM

Figure 5 shows a typical connection diagram for the AD7822,

AD7825, and AD7829. The AGND and DGND are connected

together at the device for good noise suppression. The parallel

interface is implemented using an 8-bit data bus. The end of

conversion signal (EOC) idles high, the falling edge of CONVST

initiates a conversion and at the end of conversion the falling

edge of EOC is used to initiate an Interrupt Service Routine

(ISR) on a microprocessor. (See Parallel Interface section for

more details.) VREF and VMID are connected to a voltage source

such as the AD780, while VDD is connected to a voltage source

that can vary from 4.5 V to 5.5 V. (See Table I in Analog Input

section.) When VDD is first connected, the AD7822, AD7825, and

AD7829 power up in a low current mode, i.e., power-down, with

the default logic level on the EOC pin on the AD7822 and

AD7825 equal to a low. Ensure the CONVST line is not floating

when VDD is applied, as this could put the AD7822/AD7825/

AD7829 into an unknown state. A suggestion is to tie CONVST

to VDD or DGND through a pull-up or pull-down resistor. A rising

edge on the CONVST pin will cause the AD7829 to fully power up

while a rising edge on the PD pin will cause the AD7822 and

AD7825 to fully power up. For applications where power

consumption is of concern, the automatic power-down at the

end of a conversion should be used to improve power performance.

(See Power-Down Options section of the data sheet.)

SUPPLY

4.5V TO 5.5V

10␮F

1.25V TO

3.75V INPUT

0.1␮F

2.5V

AD780

PARALLEL

INTERFACE

VDD

VREF

VMID

DB0–DB7

VIN1

EOC

AD7822/

VIN2

AD7825/

RD

AD7829

CS

VIN4(8)

AGND

CONVST

A0

A1

␮C/␮P

DGND

A2

PD

Figure 5. Typical Connection Diagram

REV. B

–7–

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