HSP50016JC-5296 데이터 시트보기 (PDF) - Intersil
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HSP50016JC-5296 Datasheet PDF : 30 Pages
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HSP50016
The Delta Phase Increment parameter can take on values
from 0 to 224 - 1 which corresponds to the Delta Phase
Increment:
0 < DeltaPhase Increment < π(2–8 – 2–32) radians
(EQ. 5)
The output of the phase accumulator forms the input to the
SIN/COS Generator which in turn produces a quadrature
vector which rotates clockwise: the outputs are cos(ωn) and
-sin(ωn). The outputs of the SIN/COS Generator are two's
complement values which are scaled to prevent overflow in
subsequent operations in the DDC under normal operation.
The scale factor has a negligible effect on the end to end
DDC gain.
The frequency resolution of the DDC = (frequency of CLK)/
(Number of Phase Register bits). At the maximum clock rate,
this results in a frequency selectivity of 75MHz/233 = 0.009Hz.
The 18-bit phase word yields a phase noise figure of greater
than 102dB.
Mixer
The Mixer performs quadrature modulation by multiplying
the output of the SIN/COS Generator by the input data. The
outputs of the I and Q multipliers are symmetrically rounded
to 17 bits to preserve the 102dB spurious free dynamic
range (SFDR). The result of the quadrature modulation
process is passed to the High Decimating Filter (HDF)
Section.
High Decimation Filter
The High Decimation Filter (HDF) Section is comprised of
two real HDF filters, one processing the I data branch and
one processing the Q data branch. Each branch has the
lowpass response shown in Figure 7. The normalized HDF
frequency impulse response is given by the equation:
H(f) = -S---S-i--n-i--n-(--π-(--π-F---F-S---S-/-R--)---) 5 R--I- 5
(EQ. 6)
where FS is the input sampling rate; R is the decimation
(rate change) factor.
Figure 7A shows this equation plotted from DC to the first
null, while Figure 7B shows the equation plotted from DC
response to fS.
NOTE: The HDF is a true FIR filter; i.e., the phase is linear.
The data path through the HDF was designed to ensure a
true 16-bit noise floor (approximately 98dB) at the output of
the DDC. The structure of the HDF filter used in the DDC is a
five stage decimation filter. The width of each successive
stage decreases such that the LSBs are lost due to
truncation [1]. As a result, the data must be processed in the
MSBs of the filter so that the noise due to truncation is below
the required noise floor. Thus, the input data of the HDF
must be shifted so that its output data fills the HDF output
word. The shift is a function of the desired HDF decimation
rate R and the number of HDF filter stages (which is fixed at
5). The shift is performed by the Data Shifter, which positions
the input data to the HDF for the maximum dynamic range
while avoiding overflow errors. The shift factor is
programmed into the Shift field of Control Word 4. The value
in this field is calculated by the equation:
Shift = 75 – Ceiling(5 log2(R))
(EQ. 7)
where R is the HDF decimation factor and Ceiling(X)
denotes the ceiling function of X; i.e., the result is X if X is an
integer, otherwise the result is the next higher integer.
During RESET, the HDF is initialized and will not output any
information until it is filled with new data.
NOTE: The output rate of the HDF is CLK divided by the
HDF decimation factor (CLK/R). The HDF decimation
counter preload (DCP) is programmed in Control Word 5,
bits 21-35 and has the value: DCP = R -I, where R is the
HDF decimation factor.
0
-20
-40
-60
-80
-100
-120
fS
fS
3fS
fS
5fS 3fS 7fS
fS
8R
4R
8R
2R
8R
4R
8R
R
FREQUENCY (Hz)
FIGURE 7A. FREQUENCY RESPONSE OF HIGH DECIMATION
FILTER FROM DC TO FIRST NULL
(FOR R = 16)
Gain (dB) = 20log [H(f)]
0
-20
-40
-60
-80
-100
-120
fS 2fS 4fS 6fS
fS 10fS 12fS 14fS fS
RR
R
R
2
R
R
R
FREQUENCY (Hz)
FIGURE 7B. DDC HC FREQUENCY RESPONSE
(FOR R = 16)
Gain (dB) = 20log[H(f)]
3-8
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