N80C151SA 데이터 시트보기 (PDF) - Intel

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N80C151SA

HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Intel 

8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER

PROGRAMMING AND VERIFYING

NONVOLATILE MEMORY

The 87C151SA SB has several areas of nonvolatile

memory that can be programmed and or verified

on-chip code memory (8 16 Kbytes) lock bits (3

bits) encryption array (128 bytes) and signature

bytes (3 bytes)

Figure 16 shows the setup for programming and or

verifying the nonvolatile memory Table 11 lists the

programming and verification operations and indi-

cates which operations apply to the different ver-

sions of the 87C151SA SB It also specifies the sig-

nals on the programming input (PROG ) and the

ports The ROM OTPROM mode (port 0) specifies

the operation (program or verify) and the base ad-

dress of the memory area The addresses (ports 1

and 3) are relative to the base address (On-chip

memory for a 16-Kbyte ROM OTPROM device is lo-

cated at address range 0000H–3FFFH The other

areas of the ROM OTPROM are outside the memo-

ry address space and are accessible only during pro-

gramming and verification )

Information in Figures 17 and 18 define the configu-

ration bits Figure 19 shows the waveforms for the

programming and verification cycles and Table 12

lists the timing specifications The signature bytes of

the 83C151SA SB ROM versions and the

87C151SA SB OTPROM versions are factory pro-

grammed Table 13 lists the addresses and the con-

tents of the signature bytes

Factory-programmed ROM and OTPROM versions

of 8XC151SA SB use configuration byte information

supplied in a separate hexadecimal disk file

8XC151SA SB devices without internal

ROM OTPROM arrays fetch configuration byte in-

formation from external application memory based

on an internal address range of FFF9 8H

NOTE

The VPP source in Figure 16 must be well regu-

lated and free of glitches The voltage on the VPP

pin must not exceed the specified maximum

even under transient conditions

28

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