N80C151SA 데이터 시트보기 (PDF) - Intel

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N80C151SA

HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Intel 

8XC151SA SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 12 Programming and Verification Modes Mode

Mode

Program On-Chip Code

Memory

Verify On-Chip Code

Memory

Program Configuration

Bytes

Verify Configuration

Bytes

Program Lock Bits

Verify Lock Bits

Program Encryption

Array

Verify Signature Bytes

8XC151SA SB

Xe7 Xe3

Y

Y

Y

Y

Y

Y

Y

Y

Y

PROG

5 Pulses

High

25 Pulses

High

25 Pulses

High

P0

68H

28H

6BH

2BH

6CH

29H

P2

Data

Data

XX

Data

Data

Data

Addresses

P1 (high) P3 (low)

0000H – 3FFFH (16K)

0000H – 1FFFH (8K)

0000H – 3FFFH (16K)

0000H – 1FFFH (8K)

0001H – 0003H

0000H

0000H – 007FH

0030H 0031H 0060H

Notes

1

2

2

13

4

1

NOTES

1 The PROG pulse waveform is shown in Figure 19

2 Factory-programmed ROM and OTPROM versions of 8XC151SA SB use configuration byte information supplied in a

separate hexadecimal disk file 8XC151SA SB devices without internal ROM OTPROM arrays fetch configuration byte

information from external application memory based on an internal address range of FFF9 8H

3 When programming the lock bits the data bits on port 2 are don’t care Identify the lock bits with the address as follows

LB3 - 0003H LB2 - 0002H LB1 - 0001H

4 The three lock bits are verified in a single operation The states of the lock bits appear simultaneously at port 2 as

follows LB3 - P2 3 LB2 - P2 2 LB1 - P2 1 High e programmed

29

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