K51P121M100SF2V2 데이터 시트보기 (PDF) - Freescale Semiconductor

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K51P121M100SF2V2

K51 Sub-Family

Freescale Semiconductor 

General

Table 9. Device clock specifications (continued)

Symbol Description

fLPTMR_pin LPTMR clock

fLPTMR_ERCLK LPTMR external reference clock

fFlexCAN_ERCLK FlexCAN external reference clock

fI2S_MCLK I2S master clock

fI2S_BCLK I2S bit clock

Min.

—

—

—

—

—

Max.

25

16

8

12.5

4

Unit

MHz

MHz

MHz

MHz

MHz

Notes

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

other module.

5.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

CMT, and I2C signals.

Table 10. General switching specifications

Symbol

Description

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

External reset pulse width (digital glitch filter disabled)

Mode select (EZP_CS) hold time after reset

deassertion

Port rise and fall time (high drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

Min.

1.5

100

16

100

2

—

—

—

—

Max.

—

—

—

—

—

12

6

36

24

Table continues on the next page...

Unit

Bus clock

cycles

ns

ns

ns

Bus clock

cycles

ns

ns

ns

ns

Notes

1, 2

3

3

3

4

K51 Sub-Family Data Sheet, Rev. 1, 6/2012.

20

Preliminary

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