IDT70V05L(1996) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT70V05L
(Rev.:1996)

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V05S/L

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns Max.

1.5V

1.5V

Figures 1and 2

2941 tbl 10

COMMERCIAL TEMPERATURE RANGE

3.3V

DATAOUT

BUSY

INT

435Ω

590Ω

30pF

3.3V

DATAOUT

435Ω

590Ω

5pF

2941 drw 05

Figure 1. AC Output Test Load

2941 drw 06

Figure 2. Output Load

(For tLZ, tHZ, tWZ, tOW)

Including scope and jig.

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)

IDT70V05X25

IDT70V05X35

Symbol

Parameter

Min.

Max.

Min.

READ CYCLE

tRC

Read Cycle Time

25

—

35

tAA

Address Access Time

tACE

Chip Enable Access Time(3)

—

25

—

—

25

—

tAOE

Output Enable Access Time

—

15

—

tOH

Output Hold from Address Change

3

tLZ

Output Low-Z Time(1, 2)

3

tHZ

Output High-Z Time(1, 2)

—

tPU

Chip Enable to Power Up Time(2)

0

tPD

Chip Disable to Power Down Time(2)

—

tSOP

Semaphore Flag Update Pulse (OE or SEM)

15

—

3

—

3

15

—

—

0

25

—

—

15

tSAA

Semaphore Address Access Time

—

35

—

NOTES:

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but not production tested.

3. To access RAM, CE = VIL, SEM = VIH.

4. "X" in part numbers indicates power rating (S or L).

Max.

—

35

35

20

—

—

20

—

35

—

45

TIMING OF POWER-UP POWER-DOWN

CE

IDT70V05X55

Min. Max. Unit

55

—

ns

—

55

ns

—

55

ns

—

30

ns

3

—

ns

3

—

ns

—

25

ns

0

—

ns

—

50

ns

15

—

ns

—

65

ns

2941 tbl 11

tPU

ICC

50%

ISB

tPD

50%

2941 drw 07

6.35

6

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