IDT70V05L(1996) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT70V05L
(Rev.:1996)

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V05S/L

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,3,5,8)

ADDRESS

OE

CE or SEM (9)

tWC

tAW

tHZ (7)

R/W

DATAOUT

DATAIN

tAS(6)

(4)

tWP(2)

tWZ(7)

tDW

tWR (3)

tOW

tDH

(4)

2941 drw 09

TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,3,5,8)

tWC

ADDRESS

CE or SEM(9)

R/W

tAS(6)

tAW

tEW (2)

tWR(3)

tDW

tDH

DATAIN

2941 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, or R/W.

7. Timing depends on which enable signal is de-asserted first, CE, or R/W.

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can

be as short as the specified tWP.

6.35

8

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