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LB1876 데이터 시트보기 (PDF) - ON Semiconductor

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LB1876 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LB1876
Continued from preceding page.
Pin No. Pin name
Function
22 PD
Phase comparator output pin.
The phase error is converted to a pulse duty and output from
this pin.
23 CLD
Phase lock signal mask time setting pin.
A mask time of about 90ms can be set by inserting a
capacitor (about 0.1μF) between this pin and ground. Leave
this pin open if there is no need to mask.
Equivalent curcuit
VREG
300Ω
22
VREG
300Ω
23
24 FGS
FG Schmitt output pin.
Open collector output.
VREG
24
25 LD
Phase lock detection output pin.
Open collector output.
VREG
Turns on (goes low) when phase lock is detected.
25
26 S/S
Start/stop control pin.
Low: 0 to 1.5V
High: 3.5V to VREG
Hysteresis: About 0.5V
Apply a low level to start; this pin goes high when open.
VREG
27 CLK
30
VCC
Clock input pin.
Low: 0 to 1.5V
High: 3.5V to VREG
Hysteresis: About 0.5 V
fCLK = 10kHz maximum
If there is noise on the clock signal, remove that noise with a
capacitor.
Power supply pin
Insert a capacitor between this pin and ground to prevent
noise from entering the IC. (Use a value of 20 or 30μF or
higher.)
VREG
22kΩ
2kΩ
26
22kΩ
2kΩ
27
Continued on next page.
No.6201-8/12

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