LV4904V-MPB-E 데이터 시트보기 (PDF) - ON Semiconductor
부품명
상세내역
제조사
LV4904V-MPB-E Datasheet PDF : 25 Pages
| |||
LV4904V
2.6 Input data format setting pins (DFORM0, DFORM1, DFORM2)
The DFORM0, DFORM1 and DFORM2 pins are set to high or low to match the data format that is input.
In the combined I2C bus and pin setting mode, the data format settings (Table 5.1.1) established according to the I2C
register are valid when DFORM0, DFORM1, and DFORM2 are low. Since the initial setting of the I2C register is I2S,
I2S is the setting that is established when DFORM0, DFORM1, and DFORM2 are low in the initial state after reset
release.
Table 2.6 shows the format settings established according to the DFORM0, DFORM1, and DFORM2 pins.
DFORM2
L
L
L
L
H
H
H
DFORM1
L
L
H
H
L
L
H
Table 2.6 Input data format settings
DFORM0
Setting
Combined I2C Bus and Pin setting Mode
Pin Setting Mode
L
I2C register setting
I2S
H
Left justified, MSB first
L
Right justified, LSB first
H
24-bit, right justified, MSB first
L
20-bit, right justified, MSB first
H
18-bit, right justified, MSB first
L
16-bit, right justified, MSB first
2.7 Master clock setting pin (MCKFS)
The MCKFS pin is set to high or low to match the rate of the master clock that is to be input from the MCK pin.
In the combined I2C bus and pin setting mode, the master clock settings (Table 8.1.2) established according to the I2C
register are valid when MCKFS is low. Since the initial setting of the I2C register is 256fs, 256fs is the setting that is
established when MCKFS is low in the initial state after reset release.
If the rate of the clock that is input from the MCK pin does not match the MCKFS pin or the setting established
according to the I2C register, an abnormal sound is generated or the output is set to off.
Table 2.7 shows the MCKFS function settings.
MCKFS
L
H
Table 2.7 MCKFS pin function settings
Setting
Combined I2C Bus and Pin setting mode
I2C register setting
Pin Setting Mode
256 fs
512 fs
2.8 Sample rate setting pin (SRATE)
The SRATE pin is set to high or low to match the sample rate of the input data.
In the combined I2C bus and pin setting mode, the sample rate settings (Table 8.1.2) established according to the I2C
register are valid when SRATE is low. Since the initial setting of the I2C register is 44.1 kHz/48 kHz, 44.1 kHz/48 kHz
is the setting that is established when SRATE is low in the initial state after reset release.
Table 2.8 shows the SRATE function settings.
SRATE
L
H
Table 2.8 SRATE pin function settings
Setting
Combined I2C Bus and Pin setting mode
I2C register setting
Pin Setting Mode
44.1 kHz/48 kHz
88.2 kHz/96 kHz
No.A1963-10/25
Share Link: 