STLC5466 데이터 시트보기 (PDF) - STMicroelectronics

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STLC5466

64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5466

III.3.3

III.3.4

III.3.5

III.4

III.5

III.6

III.6.1

III.6.2

III.6.2.1

III.6.2.2

III.6.2.3

III.7

III.7.1

III.7.2

III.7.3

III.7.4

III.7.4.1

III.7.4.2

III.7.4.3

III.7.4.4

III.8

III.9

III.9.1

III.9.2

III.10

III.10.1

III.10.2

III.10.3

III.10.4

III.10.5

III.11

III.12

III.13

IV

V

VI

VI.1

VI.2

VI.3

Structure of the Treatment ...................................................................................................20

CI and Monitor Channel Configuration..................................................................................20

CI and Monitor Transmission/Reception Command .............................................................20

SCRAMBLER AND DESCRAMBLER...................................... ............................................20

CONNECTION BETWEEN “ISDN CHANNELS” AND GCI CHANNELS ..............................20

MICROPROCESSOR INTERFACE......................................... ............................................21

Description ...........................................................................................................................21

Buffer ...................................................................................................................................21

Write FIFO ........................................................................................................................21

Read Fetch Memory .........................................................................................................23

Definition of the Interface for the different microprocessors..............................................23

MEMORY INTERFACE ........................................................... ............................................23

Function Description ............................................................................................................23

Choice of memory versus microprocessor and capacity required ........................................23

Memory Cycle .......................................................................................................................23

Memories composed of different circuits ..............................................................................23

Memory obtained with 1M x16 SDRAM circuit..................................................................23

Memory obtained with 2M x 8 SDRAM circuit...................................................................23

Memory obtained with 8M x 8 SDRAM circuit...................................................................23

Memory obtained with 4M x 16 SDRAM circuit.................................................................24

BUS ARBITRATION ................................................................ ............................................24

CLOCKS .................................................................................. ............................................24

Clock Distribution Selection and Supervision .......................................................................24

VCXO Frequency Synchronization .......................................................................................24

INTERRUPT CONTROLLER................................................... ............................................25

Description ........................................................................................................... ................25

Operating Interrupts (INT0 Pin)........................................................................................ .....25

Time Base Interrupts (INT1 Pin) ........................................................................................ ...25

Emergency Interrupts (WDO Pin) ......................................................................................... 25

Interrupt Queues ..................................................................................................................25

WATCHDOG............................................................................ ............................................25

RESET ..................................................................................... ............................................25

BOUNDARY SCAN.................................................................. ............................................26

DC SPECIFICATIONS..........................................................................................................27

LIST OF REGISTERS ..........................................................................................................29

INTERNAL REGISTERS ......................................................................................................31

IDENTIFICATION AND DYNAMIC COMMAND REGISTER... IDCR (00)H .........................31

GENERAL CONFIGURATION REGISTER 1 .......................... GCR1 (02)H........................31

INPUT MULTIPLEX CONFIGURATION REGISTER 0............ IMCR0 (04)H.......................33

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