A29L040-70 데이터 시트보기 (PDF) - AMIC Technology
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A29L040-70 Datasheet PDF : 32 Pages
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A29L040 Series
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 ( Data Polling)
and I/O6 (toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L040 is fully erased when
shipped from the factory.
Pin Configurations
n DIP
A18
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O0
13
I/O1
14
I/O2
15
VSS
16
32 VCC
31 WE
30
A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23
A10
22 CE
21
I/O7
20
I/O6
19
I/O5
18
I/O4
17
I/O3
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase
on hold for any period of time to read data from, or program
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
n PLCC
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0
13
A29L040L
29
A14
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
I/O7
n 32-pin TSOP (8mm X 20mm)
n 32-pin sTSOP (8mm X 14mm)
A11 1
A9 2
A8 3
A13 4
A14 5
A17 6
WE 7
VCC 8
A18 9
A16 10
A15 11
A12 12
A7 13
A6 14
A5 15
A4 16
A29L040V (8mm x 20mm)
A29L040X (8mm x 14mm)
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 VSS
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
PRELIMINARY (June, 2003, Version 0.1)
2
AMIC Technology, Corp.
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