IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

. 1-D/2-D SOFTWARE CONFIGURABLE CON-

VOLVER/FILTER

. ON-CHIP PROGRAMMABLE LINE DELAYS (0

— 1120 STAGES)

. 8-BIT DATA AND 8.5-BIT COEFFICIENT

SLICE

. 21 MULTIPLY-AND-ACCUMULATE STAGES

. 1-D (21) OR 2-D (3 x 7) CONVOLUTION WIN-

DOW

. ON-CHIP POST PROCESSOR FOR DATA

TRANSFORMATION

. FULLY CASCADABLE IN WINDOW SIZE AND

ACCURACY

. 20 MHZ DATA THROUGHPUT (420 MOPS)

. SIGNED/UNSIGNED DATA AND COEFFI-

CIENTS

. MICROPROCESSOR INTERFACE

. HIGH SPEED CMOS IMPLEMENTATION

. TTL COMPATIBLE

. SINGLE +5V ± 10% SUPPLY

. POWER DISSIPATION < 2.0 WATTS

. 100 PIN CERAMIC PGA

PGA100

(Ceramic Grid Array Package)

APPLICATIONS

. 1-D and 2-D digital convolution and correlation

. Real time image processing and enhancement

. Edge and feature detection

. Data transformation and histogram equalisa-

tion

. Computer vision and robotics

. Template matching

. Pulse compression

. 1-D or 2-D interpolation

ORDERING INFORMATION

Part Number

Package

Clock

Speed

IMSA110-G20S PGA100 20MHz

Military/

commercial

commercial

July 1992

1/26

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