IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

Figure 1 : IMSA110 Users Model

ENABLE 1

ENABLE 2

WRITE

MEM

DATA

ADDRESS

Asynchronous Functions

21 x 8-bit

Update coefficient registers

8

Decode

logic

21 x 8-bit

Current coefficient registers

9

Backend

look up table

256 x 8-bit data

transformation

look up RAM

USR

LSR

8

PSRIN

1120 stage Programmable

shift register (PSRC)

7-stage

multiply-accumulate

array C

Configuration and

control registers

PCR0

PCR1

PCR2

BCR

MMB

SCR

ACR

OUB

TCR

Control

logic

CLOCK

RESET

1120 stage Programmable

shift register (PSRB)

D

7-stage

multiply-accumulate

array B

PSROUT

CASCADE

INPUT

1120 stage Programmable

shift register (PSRA)

8

22

Synchronous Functions

7-stage

multiply-accumulate

array A

22

Backend

post-processing unit

(normalization, saturation,

and data transformation)

22 CASCADE

OUTPUT

The IMSA110 has five interfaces through which

data can be transferred, Figure 1. The microproc-

essor interface allows access to the coefficient

registers, the configuration and status registers,

and the data transformation tables. The remaining

four interfaces allow high speed data input and

output to the IMSA110 and the cascading of several

devices. A typical IMSA110 system is shown in

Figure 3. If N devices are used in the cascade, they

can be configured, entirely under software control,

as a 21N stage 1-D transversal filter or as a 7X by

3Y 2-D window, where X and Y are any integers

satisfying N ≤ XY. For example 4 cascaded devices

can be software configured as: an 84-stage 1-D

filter, a 7 by 12 2-D window, a 28 by 3 2-D window,

or a 14 by 6 2-D window.

The final output of the chip is 22 bits wide in twos

complement format.

Figure 2 shows the distribution of the delays inside

the part.

The latency between PSRin and COUT is depend-

ent upon the length of PSRc. For example, with

PSRc set to 0, and all coefficients set to zero except

CR0c[6] (so the data passes through all MAC

stages), the COUT bus will correspond to the

PSRin bus delayed by 47 clock cycles.

The latency between PSRin and PSRout is 5 cycles

PLUS the lengths of PSRc, PSRb and PSRa. If the

shift registers are bypassed by setting SCR[1] to 1

then PSRout will be PSRin delayed by 2 clock

cycles.

The Latency between the cascade input (CIN) and

cascade output (COUT) is 6 cycles. This is shown

lumped at the cascade input and cascade output

pads in Figure 2. Figure 4 gives details of the data

pipelining through the backend datapath.

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