IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

Figure 3 : A Typical IMSA110 Based System

General purpose

microprocessor

IMSA110

Input

PSRIN

PSROUT

IMSA110

Cascade

IN

Cascade

OUT

Clock

PSRIN

PSROUT

IMSA110

Cascade

IN

Cascade

OUT

PSRIN

PSROUT

IMSA110

Cascade

IN

Cascade

OUT

Output

3. PROGRAMMABLE SHIFT REGISTERS

The three shift registers are 8 bits wide and are

each programmable from 0 up to 1120 clock cycles

in length. The lengths are programmed into control

registers via the microprocessor interface.

Data is clocked into the device via the PSRin bus

(Programmable Shift Register in) at a maximum

rate of 20MHz. On-chip, the input data is then fed

through a pipeline of the three shift registers. The

output of the first shift register passes to the first

7-stage mac array and also to the input of the

second shift register. Having passed through all

three shift registers the data is output on the

PSRout bus and can be used for cascading. Alter-

natively, as shown in Figure 2 the shift registers can

be bypassed and the input data transferred to the

PSRout bus after two delay stages. This mode can

be controlled via the on-chip control registers and

significantly simplifies software configuration of a

cascade arrangement.

4. MAC ARRAY

As shown in Figure 2, the processing core of the

device consists of a configurable array of multiply-

accumulators (macs). The mac array consists of

three 7-stage transversal filters which can be con-

figured either as a 21-stage linear pipeline or as a

3 × 7 two-dimensional window. The input data is

8 bits wide and is fed to the mac array via three

programmable shift registers.

The output of each shift register is supplied as input

to one of the three 7-stage transversal filters. For

each of the three transversal filters the associated

input data is fed simultaneously to all 7 mac stages.

At each stage the input sample is multiplied by a

coefficient stored in memory, and added to the

output of the previous stage delayed by one clock

cycle. The output of each 7-stage mac is fed, via a

delay stage, to the first stage in the next transversal

filter.

The coefficient word width in the mac array is 8 bits

wide. Two banks of coefficients are provided. At any

instant one set of coefficients is in use within the

mac array. The set in use is defined by the state of

the ‘Current Bank’ bit, ACR[0]. The other set can be

altered via the microprocessor interface. Once a

new set of coefficients has been loaded, the activi-

ties of the two coefficient banks can be inter-

changed without interrupting the flow of data. Alter-

natively, by setting the ‘continous bank swap’ bit

SCR[0], the two coefficient banks are swapped

automatically after each data input. In this case the

‘Current Bank’ bit only determines which bank is

used first. Both data input and coefficients can be

programmed independently to support twos com-

plement or positive unsigned formats allowing mul-

tiple devices to be used as a ‘slice’ in higher accu-

racy systems.

Within the mac array no truncation or rounding is

performed on the partial products. The mac array

output is fed to the backend post-processing unit

which is responsible for data transformation / nor-

malisation and cascading function.

5. BACKEND POST-PROCESSOR — hardware

description

The Backend Post-Processor consists of four ma-

jor blocks : The input block (shifter, cascade adder

and rectifier unit),a statistics monitor,the data con-

ditioning unit which itself consists of the data trans-

formation unit and the data normaliser, and the

output block (output adder and multiplexers).

A detailed diagram of the Backend Post-Processor

is given in Figure 4.

All operations performed in the backend are on

twos complement signed numbers unless other-

wise stated.

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