IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

부품명

상세내역

제조사

IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

5.1 Shifter, Cascade Adder and Rectifier

Data from the mac array enters the datapath via a

programmable shifter. The shifter is capable of

arithmetic right shifts (divides) of up to 8 bits with

rounding, and left shifts of up to 8 bits. The size of

this shift is controlled by the status bits BCR0[5-1].

The output of the shifter passes into the cascade

adder where it is added, along with any rounding

generated by the shifter, to either the cascade input

bus (BCR0[0] = 0), or a zero value (BCR[0] = 1).

If the result of this 22-bit signed addition is greater

than 221 - 1, (209715110) then the adder will gen-

erate a positive overflow. Likewise, if it is less than

-221, (-209715210) a negative overflow will be gen-

erated. In other words, a positive overflow is gen-

erated if the result of adding two positive numbers

(both MSBs = 0) is negative (resulting MSB = 1).

Conversely, a negative overflow is generated if the

result of adding two negative numbers (both

MSBs = 1) is positive (MSB = 0). Adding two num-

bers of different signs cannot cause the adder to

overflow.

The output of the cascade adder can optionally be

full-wave or half wave rectified under the control of

BCR0[7,6]. The output of the rectifier passes onto

the X bus. Overflows on the X bus are signalled to

both the statistics monitor and the data conditioner.

5.2 Statistics Monitor

The statistics monitor allows the user to set up

watch dogs on the dynamics of the data on the X

bus. It cannot affect the data on the X bus. The

statistics gathered provide information on the sys-

tem behaviour which can be used to ensure correct

data scaling and normalisation. The information is

also useful in the control of the overall system’s

analogue frontend.

Hardware/Functions

The statistics monitor consists of a 24 bit Min/Max

register (MMR), a 24 bit Min/Max Buffer (MMB), a

22 bit Over/UnderShoot Counter (OUC), a 22 bit

Over/UnderShoot Buffer (OUB) and a 22 bit twos

complement comparator.

It can perform one of four functions :

• MAX REGISTER : Capture the maximum value

of data and store it in the MMR.

• MIN REGISTER : Capture the minimum value of

data and store it in the MMR.

• OVERSHOOT COUNTER : Increment the OUC

each time the data value exceeds the preset

value in the MMR.

• UNDERSHOOT COUNTER : Increment the OUC

each time the data value is less than the preset

value in the MMR.

The mode of operation is determined by the

Max/Min switch BCR1[0], and the Static Threshold

switch BCR1[1].

Operation

Each sample on the X bus is compared against the

threshold stored in the MMR.

If the unit is configured as an overshoot counter

and the data on the X bus exceeds the threshold in

the MMR, then the counter (OUC) is incremented.

If the data is less than or equal to the threshold, then

no action will occur. The OUC is unsigned and will

not wrap around. Thus it behaves as a saturating

counter with a maximum value of 222 - 1,

(3FFFFF16, 419430310). If there is a positive over-

flow on the X bus, then the counter will increment

since the correct X bus value must exceed the

threshold. Similarly a negative overflow on the X

bus will not increment the counter since the correct

X bus value cannot exceed the preset threshold.

If the unit is configured as an undershoot counter

then the counter will be incremented whenever the

sample is less than the preset threshold. In this

case a negative overflow will cause the counter to

increment.

If the unit is configured as a max register and the

X bus exceeds the current threshold in the MMR,

then the value on the Xbus is loaded into the MMR

and becomes the new threshold and the counter is

incremented. If the threshold is not exceeded then

no action occurs. Thus the value in the MMR is the

maximum value that has appeared on the X bus,

and the value in the OUC has been incremented by

the number of times that the threshold has been

updated.

If the unit is configured as a min register then the

threshold is updated and the counter incremented

whenever the X bus is less than the current thresh-

old.

When operating as a min/max register, overflows

on the X bus can never cause the threshold to be

updated as this would load an erroneous value into

the MMR.

6/26

Share Link: