IMSA110 데이터 시트보기 (PDF) - STMicroelectronics
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IMSA110 Datasheet PDF : 26 Pages
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IMSA110
Overflows
Bit 22 of the MMR records the history of positive
overflows on the X bus. Similarly bit 23 records the
history of negative overflows. These bits in the
MMR are set to zero by writing to the MMR copy
location and are active independently of whether
the Static Threshold bit is set. When the MMR is
read, then bits 22 and 23 are interpreted as follows:
bit 23
0
0
1
1
bit 22
0
1
0
1
condition
No overflow has occured
One or more positive overflows
have occured
One or more negative overflows
have occured
Both postive and negative
overflows have occured
Detailed block diagram of the Backend Post-proc-
essing Unit
Access to registers
The MMR and OUC are accessed, through the
memory interface, only via their associated buffers
(MMB and OUB respectively) and are not accessi-
ble directly. In order to load the MMR with a value,
the host must first write the value to the MMB and
then transfer the data from the MMB to the MMR
by performing a WRITE to the copy MMR location,
0B416. To read the MMR the host must first perform
a READ cycle from location 0B416 (which transfers
the contents of the MMR into the MMB) and then
read the MMB. The OUB is accessed in the same
way except that the dummy writes and reads are
done to and from location 0BC16.
Copies from MMR to MMB and OUC to OUB
(reads) can be performed at any time giving a
snapshot of the contents of the MMR and OUC
respectively. Copies from MMB to MMR and OUB
to OUC (writes) can also be performed at any time
allowing the threshold and counter to be updated
dynamically.
5.3 Data transformation unit
The data transformation unit consists of a presca-
lar, an under/over select detector, a look up table
and a byte selector. It can be used in isolation to
perform abitrary data mappings, or in conjunction
with the data normaliser to implement sophisticated
dynamic range compression functions.
Prescalar
This allows an 8-bit field anywhere within the 22-bit
X bus to be selected as the address to the LUT. This
is performed by right shifting the X bus so that the
required 8 bits are at the least significant end. The
8/26
amount of right shift is programmed in BCR2[4-0]
and can have a value from 0 to 16.
Over/under select detector
With PosLUTAddr (SCR[6]) set to zero, this unit
monitors whether the amount of right shift per-
formed by the prescalar is sufficient to include all
significant bits in, and maintain the sign of, the
selected 8 bit field (i.e. an over or under select is
generated if the most significant bit of the selected
8 bit field differs from any subsequent bit right up to
and including the most significant bit of the right
shifted X bus). This will be an overselect if the X
bus is positive (Bit 21 = 0), and an underselect if
the X bus is negative (Bit 21 = 1). In other words
the LUT address is always deemed to be signed
with an address range of -128 to 127.
If however the control bit PosLUTAddr (SCR[6]) is
set to one, the unit monitors whether the amount of
right shift performed by the prescaler is sufficient to
include all significant bits in the selected 8 bit field
AND that all unselected bits are zero (i.e. an over
or under select is generated if the first selected bit
(bit 9) is not zero OR differs from any subsequent
bit right up to and including the most significant bit
of the right shifted X bus). This will be an overselect
if the Xbus is positive and an underselect WHEN-
EVER the Xbus is negative. Thus, in this mode, the
address range of the LUT is 0 to 255.
Prescalar under/over selects and X bus posi-
tive/negative overflows are passed to the LUT
along with the selected 8 bit address field.
Look up table (LUT) and byte select
The LUT consists of 64 words, 32 bits wide plus two
special 32 bit locations called the upper and lower
saturation registers (USR and LSR respectively).
Thus the LUT is actually 66 words by 32 bits. The
32 bit output of the LUT is called the Y bus.
The most significant 6 bits of the 8 bit address field
are used to address one of 64 words in the LUT.
The least significant pair of bits in the 8 bit field are
used to control a byte select on the output. Thus in
addition to operating as a 64+2 word look up table
of 32 bit words, it can be used as an 8 bit, 256+2
byte LUT providing 8bit — 8bit transformations.
Positive overflows on the X bus, and over selects
in the prescalar cause the LUT to access the USR
overriding the address given by the prescalar. Like-
wise negative overflows and under selects cause
the LUT to access the LSR. Any sort of overflow on
the X bus or prescalar will cause the byte select
control to be overridden and the most significant
byte (byte 3) of the appropriate Saturation Register
will appear on the byte wide output of the data
transformation unit.
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