IMSA110 데이터 시트보기 (PDF) - STMicroelectronics

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IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

If there are simultaneous overflows on the X bus

and in the prescalar then the overflow from the X

bus takes priority.

The USR and LSR can thus be used to model the

saturating behaviour of analogue circuits instead of

the usual ‘wrap around’ encountered in digital sys-

tems. Alternatively the USR and LSR could signal

error conditions within the backend directly on the

output pins via one of the output multiplexers.

The LUT is loaded via the memory interface. The

addressing for the LUT corresponds to the 8 bit

field, assuming that the byte selector is being used.

In order to access the look up table, USR and LSR

from the microprocessor interface, the LUT Ac-

cess control bit ACR[1] must be set to zero. This

will force the Y bus to zero and the normaliser to be

controlled by BCR3[7-3] regardless of the setting of

the dynamic normalisation bit, BCR3[2]. The LUT,

USR and LSR can then be loaded with any arbitrary

value via the microprocessor interface. Setting the

LUT access control bit to one will then allow the LUT

to be used in the data transformation unit.

5.4 Data normaliser

This unit consists of a shifter capable of right shifts

of up to 14 bits and left shifts up to 2 bits, followed

by a zero data unit and an adder. The shifter is

controllable from one of two 5 bit sources : control

bits BCR3[7-3] or bits 26 to 22 of the Y bus. The

cont rol bit Enable Dynamic Normalisation

(BCR3[2]) determines which source is in control of

the normaliser. If this bit is set to zero the normaliser

is controlled by BCR3[7-3]. The five bit field is a

twos complement number between 14 and -2. This

indicates the amount of right shift (negative mean-

ing left shift). Any value outside this range causes

the output of the shifter to be forced to zero. The

output of the shifter, with any rounding generated

by the shifter, goes into the output adder.

5.5 Output adder

This is a 22 bit adder with one of its inputs coming

from the data normaliser. The other input is either

bits 21 to 0 of the Y bus from the data transformation

unit, or set to zero under the control of BCR3[1].

Note that any overflow occuring due to left shifting

in the normaliser or the subsequent addition in the

output adder is not detected by the IMSA110.

5.6 Output multiplexers

These two multiplexers allow the currently selected

byte from the LUT to be optionally selected to drive

either the most significant byte and/or the least

significant byte of the Cascade Output pins. This is

controlled by the state of BCR2[5] and BCR2[6].

Enabling either of these multiplexers overrides the

state of the Cascade Output pins only on the re-

lavent 8 pins. The remaining pins will continue to

represent the output of the output adder.

6. BACKEND POST-PROCESSOR — Modes of

Operation

The backend post-processing unit is capable of

performing many functions including data scaling,

transformation, dynamic range compression and

histogram equalisation.

6.1 Default mode (after Reset)

At power up or after reset the state of the backend

post-processor is such that data from the MAC

array and the cascade input are added and pass

straight through the datapath unaffected.

The default mode for the statistics monitor is min

register although the values in the OUB, OUC,

MMR and MMB will be undefined. Likewise the

contents of the LUT, USR and LSR will be unde-

fined, the LUT Access control bit will be zero

forcing the Y bus to zero and allowing the micro-

processor interface to access the LUT, USR and

LSR.

Note that the cascade output pins and the PSR

output pins are tristated.

6.2 Cascade adder / MAC data scalar

These units allow the cascading of IMS A110s

where the output of the MAC array may be scaled

before it is added to the cascade input data. The

shifter can also be used for combining devices to

obtain extended precision in input data, coefficient

word length or both.

The ability to zero the cascade input provides a

simple means of controlling the number of ‘active’

devices cascaded as well as a means of debugging

large systems.

6.3 Rectification

Rectification, the removal of negative results, is

needed in several image processing functions.

For example, edge detection using a Sobel opera-

tor usually requires full wave rectification due to the

different signs obtained at differing edge transi-

tions. Edge detection using a Laplacian operator

produces a change of sign at an edge. In this case,

removing negative numbers using half wave recti-

fication can produce better results as full wave

rectification can lead to some blurring of the edge

transition.

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