MX839 데이터 시트보기 (PDF) - CML Microsystems Plc
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MX839 Datasheet PDF : 20 Pages
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Digitally Controlled Analog I/O Processor
10
MX839 PRELIMINARY INFORMATION
4.7.2 CLOCK CONTROL Register (Hex Address $D0)
This register controls the A/D clock divide ratio:
Bits 7 to 3
DIVIDER
(Bit 2 - Bit 0)
Reserved for future use. These bits should be set to '0'.
The Xtal input clock divide ratio, which sets the A/D sample clock frequency, is defined in the
following table.
Table 5: CLOCK CONTROL Register (Hex Address $D0)
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
Function
Powersave
y1
y2
y4
y8
y16
y32
y64
Table 6: DIVIDER (Bit 2 - Bit 0)
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
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