NTE7133 데이터 시트보기 (PDF) - NTE Electronics
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NTE7133 Datasheet PDF : 7 Pages
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Functional Description (Cont’d):
PLL2 Phase Detector
This pahse detector is similar to the PLL1 phase detector. Line flyback signals (Pin2) are compared
with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are com-
pensated by adjusting the phase relationship between horizontal sync and horizontal output pulses.
A certain amount of phase adjustment is possible by injecting a DC current froma an external source
into the PLL2 filter capacitor on Pin20.
Horizontal Driver
This open–collector output stage (Pin3) can directly drive an external driver transistor. The saturation
voltage is 300mV at 20mA. To protect the line deflection transistor, the horizontal output stage does
not conduct at VP < 6.4V (Pin1).
Vertical Oscillator and Amplitude Control
This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions.
The free–running frequency fo is determined by the values of RVOS and CVOS. The recommended
values should be altered marginally only to preserve the excellent linearity and noise performance.
The vertical drive currents I5 and I6 are in relation to the value of RVOS. Therefore, the oscillator fre-
quency must be determined only by CVOS on Pin16.
fo =
1
10.8 x RVOS x CVOS
To acheive a stabilized amplitude the free–running frequency fo (without adjustment) must be lower
than the lowest occurring sync frequency. The contributions shown in Table 1 can be assumed.
Table 1. Calculation of fo Total Spread
Contributing Elements
%
Minimum Frequency Offset Between fo and the Lowest Trigger Frequency
10
Spread of IC
±3
Spread of R (22kΩ)
±1
Spread of C (0.1µF)
±5
Total
19
Results for 50 to 110Hz application: fo =
50Hz
1.19
= 42Hz
Table 2. VGA Modes
Mode
Horizontal/Vertical
Sync Polarity
1
+/–
2
–/+
3
–/–
4
+/+
Autosync
*/*
Horizontal
Frequency
(kHz)
31.45
31.45
31.45
Fixed by External Circuitry
Fixed by External Circuitry
Vertical
Frequency
(Hz)
70
70
60
–
–
Number of
Active Lines
350
400
480
–
–
Output
Mode Pin7
LOW
LOW
LOW
HIGH
Forced to GND
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