T8100 데이터 시트보기 (PDF) - Intel

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T8100

Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process for Platforms Based on Mobile Intel® 965 Express Chipset Family

Intel 

Figures

1 Core Low-Power States .............................................................................................12

2 Package Low-Power States ........................................................................................13

3 C6 Entry Sequence ...................................................................................................18

4 C6 Exit Sequence .....................................................................................................18

5 Active VCC and ICC Loadline Standard Voltage and Extreme Edition Processors ................33

6 Deeper Sleep VCC and ICC Loadline Standard Voltage and Extreme Edition Processors ......34

7 6-MB and 3-MB on 6-MB Die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ........38

8 6-MB and 3-MB on 6-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ........39

9 6-MB and 3-MB on 6-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)........40

10 6-MB and 3-MB on 6-MB die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ........41

11 3-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ........................................42

12 3-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ........................................43

13 3-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ........................................44

14 3-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ........................................45

15 Processor Pinout (Top Package View, Left Side) ............................................................46

16 Processor Pinout (Top Package View, Right Side) ..........................................................47

Tables

1 Coordination of Core Low-Power States at the Package Level..........................................13

2 Voltage Identification Definition ..................................................................................23

3 BSEL[2:0] Encoding for BCLK Frequency......................................................................27

4 FSB Pin Groups ........................................................................................................28

5 Processor Absolute Maximum Ratings..........................................................................29

6 Voltage and Current Specifications for the Extreme Edition Processors .............................30

7 Voltage and Current Specifications for the Dual-Core Standard Voltage Processors ............32

8 FSB Differential BCLK Specifications ............................................................................34

9 AGTL+ Signal Group DC Specifications ........................................................................35

10 CMOS Signal Group DC Specifications..........................................................................36

11 Open Drain Signal Group DC Specifications ..................................................................36

12 Pin Listing by Pin Name .............................................................................................48

13 Pin Listing by Pin Number ..........................................................................................55

14 Signal Description.....................................................................................................62

15 Power Specifications for the Extreme Edition Processor ..................................................71

16 Power Specifications for Dual-Core Standard Voltage Processors .....................................72

17 Thermal Diode Interface ............................................................................................73

18 Thermal Diode Parameters using Transistor Model ........................................................74

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Datasheet

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