CMX218S1 데이터 시트보기 (PDF) - CML Microsystems Plc
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CMX218S1 Datasheet PDF : 34 Pages
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ISDN Data and Telephony Protocol Engine (no X.25)
CMX218
1.3 Signal List
S1 Package
80QFP
Signal
Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
SCL
SDA
ISDNRST
RI1
DCD1
CTS1
RSTN
DVDD1
XTALN
XTAL
DVSS1
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
STN
LED9
WRN
RDN
A19
A18
A17
A16
A15
Type
O/P
BI
O/P
O/P
O/P
O/P
I/P
Power
O/P
I/P
Power
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
EEPROM - Serial Clock
EEPROM - Serial Data
ISDN S-interface Chip Reset
RS232 Port1 Ring Indicator (high when inactive)
RS232 Port1 Data Carrier Detect (high when inactive)
RS232 Port1 Clear To Send (high when inactive)
CMX218 Chip Reset (active low)
The digital positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be
decoupled to DVSS by a capacitor
The output of the on-chip Xtal oscillator inverter
The input to the oscillator inverter from the Xtal circuit
The digital negative supply rail (ground)
POTS Port Off-Hook Indicator (HK1)
RS232 Port 1 Auto-Answer Indicator (AA)
RS232 Port 1 Data Carrier Detect Indicator (DCD)
RS232 Port 1 Ready To Send Indicator (RTS)
RS232 Port 1 Receive Data Indicator (RXD)
RS232 Port 1 Transmit Data Indicator (TXD)
RS232 Port 1 Data Terminal Ready Indicator (DTR)
ISDN Line Activated Indicator (AR)
Watchdog Timer Stimulus
POTS Port Call Connected Indicator (CN1)
Memory Write Access Strobe
Memory Read Access Strobe
Memory and Peripheral Address Bus
Memory and Peripheral Address Bus
Memory and Peripheral Address Bus
Memory and Peripheral Address Bus
Memory and Peripheral Address Bus
© 1999 Consumer Microcircuits Limited
5
© 1999 Chiron Technology Limited
D/218/1
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