HY27UV08BG5M 데이터 시트보기 (PDF) - Hynix Semiconductor

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HY27UV08BG5M

32Gb NAND FLASH

Hynix Semiconductor 

1

Preliminary

HY27UV08BG(5/D/F)M Series

32Gbit (4Gx8bit) NAND Flash

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

L(1)

L(1)

L(1)

L(1)

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30(2)

A31(3)

L(1)

L(1)

L(1)

L(1)

Table 3: Address Cycle Map(x8)

NOTE:

1. L must be set to Low.

2. 4CE

3. 2CE

FUNCTION

PAGE READ

READ ID

RESET

PAGE PROGRAM (start)

MULTI PLANE

PAGE PROGRAM

BLOCK ERASE

MULTI PLANE

BLOCK ERASE

READ STATUS REGISTER

RANDOM DATA INPUT

RANDOM DATA OUTPUT

1st CYCLE

00h

90h

FFh

80h

2nd CYCLE

30h

-

-

10h

3rd CYCLE

-

-

-

-

4th CYCLE

-

-

-

-

Acceptable command

during busy

Yes

80h

11h

81h

10h

60h

D0h

-

-

60h

60h

D0h

-

70h

-

-

-

Yes

85h

-

-

-

05h

E0h

-

-

Table 4: Command Set

Rev 0.0 / Sep. 2006

9

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