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UDA1334ATS

Low power audio DAC with PLL

NXP Semiconductors. 

NXP Semiconductors

Low power audio DAC with PLL

Product specification

UDA1334ATS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334ATS incorporates a PLL capable of

generating the system clock. The UDA1334ATS can

operate in 2 modes:

• It operates as an asynchronous DAC, which means the

device regenerates the internal clocks using a PLL from

the incoming WS signal. This mode is called audio

mode.

• It generates the internal clocks from a 27 MHz clock

input, based on 32, 48 and 96 kHz sampling

frequencies. This mode is called video mode.

In video mode, the digital audio input is slave, which

means that the system must generate the BCK and

WS signals from the output clock available at pin CLKOUT

of the UDA1334ATS. The digital audio signals should be

frequency locked to the CLKOUT signal.

Remarks:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O

data interface

2. For LSB-justified formats it is important to have a WS

signal with a duty factor of 50%.

8.1.1 AUDIO MODE

Audio mode is enabled by setting pin PLL0 to LOW.

De-emphasis can be activated via pin DEEM/CLKOUT

according to Table 5.

In audio mode, pin SYSCLK/PLL1 is used to set the

sampling frequency range as given in Table 1.

Table 2 Clock output selection in video mode

PLL0

MID

HIGH

LOW

SELECTION

12.228 MHz clock; note 1

18.432 MHz clock; note 2

audio mode

Notes

1. The supported sampling frequencies are:

96, 48 and 24 kHz or 64, 32 and 16 kHz.

2. The supported sampling frequencies are:

96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz.

8.2 Interpolation filter

The interpolation digital filter interpolates from 1fs to 64fs

by cascading FIR filters (see Table 3).

Table 3 Interpolation filter characteristics

ITEM

Pass-band ripple

Stop band

Dynamic range

CONDITION

0fs to 0.45fs

>0.55fs

0fs to 0.45fs

VALUE (dB)

±0.02

−50

>114

8.3 Noise shaper

The 5th-order noise shaper operates at 64fs. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using a

Filter Stream DAC (FSDAC).

Table 1 Sampling frequency range in audio mode

SYSCLK/PLL1

LOW

HIGH

SELECTION

fs = 16 to 50 kHz

fs = 50 to 100 kHz

8.1.2 VIDEO MODE

In video mode, the master clock is a 27 MHz external clock

(as is available in video environment). A clock-out signal is

generated at pin DEEM/CLKOUT. The output frequency

can be selected using pin PLL0. The output frequency is

either 12.228 MHz (256 × 48 kHz) with pin PLL0 being at

MID level or 18.432 MHz (384 × 48 kHz) with pin PLL0

being HIGH, as given in Table 2.

2000 Jul 31

7

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