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PSD853F5VA-90J 데이터 시트보기 (PDF) - STMicroelectronics

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PSD853F5VA-90J Datasheet PDF : 128 Pages
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PSD8XXFX
Flash in-system programmable (ISP)
peripherals for 8-bit MCUs, 5 V
Features
Flash in-system programmable (ISP)
peripheral for 8-bit MCUs
Dual bank Flash memories
– Up to 2 Mbit of primary Flash memory (8
uniform sectors, 32K x8)
– Up to 256 Kbit secondary Flash memory (4
uniform sectors)
– Concurrent operation: read from one
memory while erasing and writing the other
Up to 256 Kbit SRAM
27 reconfigurable I/Oports
Enhanced JTAG serial port
PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
27 individually configurable I/O port pins
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
open-drain outputs.
In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
full-chip in-system programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
Page register
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
PQFP52 (M)
PLCC52 (J)
TQFP64 (U)
Programmable power management
Packages are ECOPACK®
Table 1. Device summary
Reference
Part number
PSD813F2
PSD813F4
PSD813F5
PSD8XXFX
PSD833F2
PSD834F2
PSD853F2
PSD854F2
May 2009
Doc ID 7833 Rev 7
1/128
www.st.com
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