NJ88C33 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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NJ88C33

Frequency Synthesiser (I2C BUS Programmable)

Zarlink Semiconductor Inc 

VCO Driving Without Voltage Doubler

To switch off the voltage doubler, bit 7 of the status register

is programmed low. This will reduce current consumption and

minimise noise. The voltage doubler output C should be

connected to GND1 as connection to GND2 would induce

noise in the VCO loop.

NJ88C33

VCO Driving With Voltage Doubler

The voltage doubler is switched on by setting bit 7 of the

status register high. It is recommended that a reservoir

capacitor of at least 1µF be connected from C to GND1.

The voltage doubler is designed to boost VCO drive in low

voltage applications.

Fig. 9 Driving a VCO without voltage doubler

Further Applications Information

A stand-alone programmer card and an evaluation board

are available for evaluating the NJ88C33. The programmer

card allows two sets of variables to be programmed into both

the divider and status registers during alternate programming

cycles, at either the standard I2C bus rate of 100kHz or at

2MHz.

Initialisation is with either a manual push-button or by an

external logic level pulse; a synchronisation output is provided

to allow a quick assessment of ‘step’ and ‘settle’ responses to

be made.

Fig. 10 Driving a VCO using the voltage doubler

The NJ88C33 evaluation board (Fig. 11 ) dernonstrates

the preferred layout technique - providing a reference

oscillator, a 60 to 80MHz VCO and a simple loop filter to

complete a minimal frequency synthesiser loop. The two units

allow analysis of different loop variables as well as the

selection of comparison frequencies for fast frequency-

hopping loops.

Application Note: AN94, ‘Using the NJ88C33 PLL

Synthesiser’ explains the design equations and

demonstrates the use of the device, and is available from your

local Zarlink Semiconductor customer service centre.

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