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SAA7102E 데이터 시트보기 (PDF) - NXP Semiconductors.

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SAA7102E
NXP
NXP Semiconductors. NXP
SAA7102E Datasheet PDF : 84 Pages
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 4:
Symbol
VDDA2
TRST
TDI
VSSD2
VDDD2
PD4
PD5
PD6
PD7
Pin description …continued
Pin
Type [1] Description
LBGA156 QFP44
B6, D6 36
S
analog supply voltage 2 (3.3 V for DACs and
oscillator)
A4
37
I
test reset input for BST; active LOW [2] [4] [5]
B5
38
I
test data input for BST [2]
C5, D5 39
S
digital ground 2
D4
40
S
digital supply voltage 2 (3.3 V for core)
A3
41
I
MSB 3 with CB-Y-CR 4 : 2 : 2;
see Table 28 to Table 33 for pin assignment
B3
42
I
MSB 2 with CB-Y-CR 4 : 2 : 2;
see Table 28 to Table 33 for pin assignment
B4
43
I
MSB 1 with CB-Y-CR 4 : 2 : 2;
see Table 28 to Table 33 for pin assignment
A2
44
I
MSB with CB-Y-CR 4 : 2 : 2;
see Table 28 to Table 33 for pin assignment
[1] Pin type: I = input, O = output, S = supply.
[2] In accordance with the “IEEE1149.1” standard the pins TDI, TMS, TCK and TRST are input pins with an
internal pull-up resistor and TDO is a 3-state output pin.
[3] Pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.
[4] For board design without boundary scan implementation connect TRST to ground.
[5] This pin provides easy initialization of the BST circuit. TRST can be used to force the Test Access Port
(TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
7. Functional description
SAA7102_SAA7103_4
Product data sheet
The digital video encoder encodes digital luminance and color difference signals
(CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or
CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported.
The SAA7102; SAA7103 can be directly connected to a PC video graphics controller with
a maximum resolution of 800 × 600 at a 50 Hz or 60 Hz frame rate. A programmable
scaler scales the computer graphics picture so that it will fit into a standard TV screen with
an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with
an adjustable anti-flicker filter for a flicker-free display at a very high sharpness.
Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input format (using 8 pins with double
edge clocking), other CB-Y-CR and RGB formats are also supported; see
Table 28 to Table 33.
A complete 3 × 256 bytes Look-Up Table (LUT), which can be used, for example, as a
separate gamma corrector, is located in the RGB domain; it can be loaded either through
the video input port Pixel Data (PD) or via the I2C-bus.
The SAA7102; SAA7103 supports a 32-bit × 32-bit × 2-bit hardware cursor, the pattern of
which can also be loaded through the video input port or via the I2C-bus.
It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the
anti-flicker filter, and in most cases the scaler, will simply be bypassed.
Rev. 04 — 18 January 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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