SAA7102E 데이터 시트보기 (PDF) - NXP Semiconductors.
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SAA7102E Datasheet PDF : 84 Pages
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
7.1 Reset conditions
To activate the reset a pulse at least of 2 crystal clocks duration is required.
During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC,
CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set
to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and
sets it into receive condition.
After reset, the state of the I/Os and other functions is defined by the strapping pins until
an I2C-bus access redefines the corresponding registers; see Table 5.
Table 5: Strapping pins
Pin
Tied
FSVGC
LOW
HIGH
VSVGC
LOW
HIGH
CBO
LOW
HIGH
HSVGC
LOW
HIGH
TTXRQ_XCLKO2 LOW
HIGH
Preset
NTSC M encoding, PIXCLK fits to 640 × 480 graphics input
PAL B/G encoding, PIXCLK fits to 640 × 480 graphics input
4 : 2 : 2 Y-CB-CR graphics input (format 0)
4 : 4 : 4 RGB graphics input (format 3)
input demultiplex phase: LSB = LOW
input demultiplex phase: LSB = HIGH
input demultiplex phase: MSB = LOW
input demultiplex phase: MSB = HIGH
slave (FSVGC, VSVGC and HSVGC are inputs, internal color bar is
active)
master (FSVGC, VSVGC and HSVGC are outputs)
7.2 Input formatter
The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR,
to a common internal RGB or Y-CB-CR data stream.
When double-edge clocking is used, the data is internally split into portions PPD1 and
PPD2. The clock edge assignment must be set according to the I2C-bus control bits
EDGE1 and EDGE2 for correct operation.
If Y-CB-CR is being applied as a 27 MB/s data stream, the output of the input formatter can
be used directly to feed the video encoder block.
7.3 RGB LUT
The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus
it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the
event that the indexed color data is applied, the RAMs are addressed in parallel.
The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data
input through the PD port. In the latter case, 256 bytes × 3 bytes for the R, G and B LUT
are expected at the beginning of the input video line, two lines before the line that has
been defined as first active line, until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT data, and so on.
SAA7102_SAA7103_4
Product data sheet
Rev. 04 — 18 January 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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