LC72725KVS 데이터 시트보기 (PDF) - ON Semiconductor

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LC72725KVS

RDS Demodulation IC

ON Semiconductor 

LC72725KVS

Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be

low level.

2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next

read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped.

3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL.

4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the

memory, READY signal goes high again.

5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a

reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied,

reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after

the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not

detected.

6. The readout mode may be switched between master and slave modes during readout.

Applications must observe the following points to assure data continuity during this operation.

1) Data acquisition timing in master made

Data must be read on the falling edge of RDCL

2) Timing of the switch from master mode to slave mode

After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE

high immediately.

Then, the microcontroller starts output by setting the RDCL signal low.

The microcontroller RDCL output must start within 840μs (tms) after RDCL went low.

In this case, if the last data read in master mode was data item n, then data starting with item n+1

will be written to memory.

3) Timing of the switch from slave mode to master mode

After all data has been read from memory and READY has gone high, the application must then wait

until READY goes low once again the next time (timing A in the figure), immediately read out one bit of

data and input the RDCL clock.

Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set

MODE low.

The application must switch MODE to low within 840μs (tms) after READY goes low (timing A in the

figure).

RDCL (microcontroller status)

RDCL (IC status)

RDCL

tm s

INPUT

OUTPUT

OUTPUT

INPUT

undefined

INPUT

OUTPUT

MODE

READY

Timing A

ts m

RDDA n-2 n-1 n

n+1

m m+1 m+2

No.A1744-8/9

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