UDA1351TS/N1,512 데이터 시트보기 (PDF) - NXP Semiconductors.

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UDA1351TS/N1,512

96 kHz IEC 958 audio DAC

NXP Semiconductors. 

Philips Semiconductors

96 kHz IEC 958 audio DAC

Product specification

UDA1351TS

1 FEATURES

1.1 General

• 2.7 to 3.6 V power supply

• Integrated digital filter and Digital-to-Analog Converter

(DAC)

• Master-mode data output and input interface for off-chip

sound processing

• 256fs system clock output

• 20-bit data path in interpolator

• High performance

• No analog post filtering required for DAC

• Support sampling frequencies from 28 kHz up to

100 kHz

• The UDA1351TS is fully pin and function compatible

with the UDA1350ATS.

1.2 Control

Controlled either by means of static pins or via the

L3 microcontroller interface.

1.3 IEC 958 input

• On-chip amplifier for converting IEC 958 input to CMOS

levels

• Lock indication signal available on pin LOCK

• Lock indication signal combined on-chip with the Pulse

Code Modulation (PCM) status bit; when non-PCM is

detected, pin LOCK indicates out-of-lock

• Key channel-status bits available via L3 interface (lock,

pre-emphasis, audio sample frequency, two channel

PCM indication and clock accuracy).

2 APPLICATIONS

Digital audio systems.

3 GENERAL DESCRIPTION

Available in two versions:

• UDA1351TS:

– only IEC 958 input to DAC in SSOP28 package.

• UDA1351H:

– full featured version in QFP44 package.

The UDA1351TS is a single chip IEC 958 audio decoder

with an integrated stereo DAC employing bitstream

conversion techniques.

A lock indication signal is available on pin LOCK,

indicating that the IEC 958 decoder is locked. This pin is

also used to indicate whether PCM data is applied to the

input or not. When non-PCM data is detected, the device

indicates out-of-lock.

By default, the DAC output and the data output interface

are muted when the decoder is out-of-lock. However, this

setting can be overruled in the L3 control mode.

1.4 Digital sound processing and DAC

• Automatic de-emphasis when using IEC 958 input with

32.0, 44.1 and 48.0 kHz audio sample frequencies

• Soft mute by means of a cosine roll-off circuit selectable

via pin MUTE or the L3 interface

• dB linear volume control with 1 dB steps from 0 dB to

−60 dB and −∞ dB

• Bass boost and treble control in L3 control mode

• Interpolating filter (fs to 128fs) by means of a cascade of

a recursive filter and a FIR filter

• Third order noise shaper operating at 128fs generates

the bitstream for the DAC

• Filter Stream DAC (FSDAC).

2001 Feb 05

3

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