UDA1351TS/N1,512 데이터 시트보기 (PDF) - NXP Semiconductors.

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UDA1351TS/N1,512

96 kHz IEC 958 audio DAC

NXP Semiconductors. 

Philips Semiconductors

96 kHz IEC 958 audio DAC

Product specification

UDA1351TS

8.3 Auto mute

By default, the DAC outputs will be muted until the IC is

locked, regardless of the level on pin MUTE (in static

mode) or the state of bit MT of the sound feature register

(in L3 mode). In this way, only valid data will be passed to

the outputs. This mute is done in the SPDIF interface and

is a hard mute, not a cosine roll-off mute.

If needed, this muting can be bypassed by setting

bit AutoMT to logic 0 via the L3 interface. As a result, the

IC will no longer mute during out-of-lock situations.

8.4 Data path

The UDA1351TS data path consists of the IEC 958

decoder, the audio feature processor, digital interpolator

and noise shaper and the DACs.

8.4.1 IEC 958 INPUT

The UDA1351TS IEC 958 decoder features an on-chip

amplifier with hysteresis, which amplifies the IEC 958 input

signal to CMOS level (see Fig.5).

All 24 bits of data for left and right are extracted from the

input bitstream as well as several of the IEC 958 key

channel-status bits.

handbook, halfpage

75 Ω

10 nF SPDIF 13

180 pF

UDA1351TS

MGU034

The extracted key parameters are:

• Pre-emphasis

• Audio sample frequency

• Two-channel PCM indicator

• Clock accuracy.

Both the lock indicator and the key channel status bits are

accessible via the L3 interface.

The UDA1351TS supports the following sample

frequencies and data bit rates:

fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s

fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s

fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s

fs = 64.0 kHz, resulting in a data rate of 4.096 Mbits/s

fs = 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s

fs = 96.0 kHz, resulting in a data rate of 6.144 Mbits/s.

The UDA1351TS supports timing levels I, II and III, as

specified by the IEC 958 standard.

8.4.2 AUDIO FEATURE PROCESSOR

The audio feature processor automatically provides

de-emphasis for the IEC 958 data stream in the static pin

control mode and default mute at start-up in the L3 control

mode.

When used in the L3 control mode, it provides the

following additional features:

• Volume control, using 6 bits

• Bass boost control, using 4 bits

• Treble control, using 2 bits

• Mode selection of the sound processing bass boost and

treble filters: flat, minimum and maximum

• Soft mute control with raised cosine roll-off

• De-emphasis selection of the incoming data stream for

fs = 32.0, 44.1 and 48.0 kHz.

Fig.5 IEC 958 input circuit and typical application.

8.4.3 INTERPOLATOR

The UDA1351TS includes an on-board interpolating filter

which converts the incoming data stream from 1fs to 128fs

by cascading a recursive filter and a FIR filter.

2001 Feb 05

9

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