WM8731SEDS/RV 데이터 시트보기 (PDF) - Cirrus Logic

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WM8731SEDS/RV

Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

Cirrus Logic 

WM8731 / WM8731L

Production Data

PIN DESCRIPTION

28 PIN

SSOP

28 PIN

QFN

NAME

TYPE

DESCRIPTION

1

5

DBVDD

Supply

Digital Buffers VDD

2

6

CLKOUT

Digital Output

Buffered Clock Output

3

7

BCLK

Digital Input/Output Digital Audio Bit Clock, Pull Down, (see Note 1)

4

8

DACDAT

Digital Input

DAC Digital Audio Data Input

5

9

DACLRC

Digital Input/Output DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)

6

10

ADCDAT

Digital Output

ADC Digital Audio Data Output

7

11

ADCLRC

Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)

8

12

HPVDD

Supply

Headphone VDD

9

13

LHPOUT

Analogue Output

Left Channel Headphone Output

10

14

RHPOUT

Analogue Output

Right Channel Headphone Output

11

15

HPGND

Ground

Headphone GND

12

16

LOUT

Analogue Output

Left Channel Line Output

13

17

14

18

ROUT

AVDD

Analogue Output

Supply

Right Channel Line Output

Analogue VDD

15

19

AGND

Ground

Analogue GND

16

20

VMID

Analogue Output

Mid-rail reference decoupling point

17

21

MICBIAS

Analogue Output

Electret Microphone Bias

18

22

MICIN

19

23

RLINEIN

Analogue Input

Analogue Input

Microphone Input (AC coupled)

Right Channel Line Input (AC coupled)

20

24

LLINEIN

21

25

MODE

Analogue Input

Digital Input

Left Channel Line Input (AC coupled)

Control Interface Selection, Pull Up (see Note 1)

22

26

CSB

Digital Input

3-Wire MPU Chip Select/ 2-Wire MPU interface address

selection, active low, Pull up (see Note 1)

23

27

SDIN

Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input

24

28

SCLK

25

1

XTI/MCLK

26

2

XTO

Digital Input

Digital Input

Digital Output

3-Wire MPU Clock Input / 2-Wire MPU Clock Input

Crystal Input or Master Clock Input (MCLK)

Crystal Output

27

3

28

4

DCVDD

DGND

Supply

Ground

Digital Core VDD

Digital GND

Note:

1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.

2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.

w

PD, Rev 4.9, October 2012

5

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