WM8778SEDS/RV 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8778SEDS/RV Datasheet PDF : 52 Pages
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Production Data
WM8778
ADCBCLK/
DACBCLK
(Output)
ADCLRC/
DACLRC
(Outputs)
DOUT
DIN
tDL
tDDA
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADC/DACLRC propagation
tDL
delay from ADC/DACBCLK
falling edge
DOUT propagation delay
tDDA
from ADCBCLK falling edge
DIN setup time to
tDST
DACBCLK rising edge
DIN hold time from
tDHT
DACBCLK rising edge
TEST CONDITIONS
Table 2 Digital Audio Data Timing – Master Mode
MIN
TYP
MAX
UNIT
0
10
ns
0
10
ns
10
ns
10
ns
DIGITAL AUDIO INTERFACE – SLAVE MODE
DACBCLK
ADCBCLK
WM8776 ADCLRC
CODEC DACLRC
DOUT
DIN
DVD
Controller
Figure 4 Audio Interface – Slave Mode
w
PD, Rev 4.2, July 2008
9
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