XRT83VSH316(2009) 데이터 시트보기 (PDF) - Exar Corporation

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XRT83VSH316
(Rev.:2009)

16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

XRT83VSH316

16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.1

4.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE ................................................................................. 36

4.7 DMO (DIGITAL MONITOR OUTPUT, LINE SIDE ONLY) .............................................................................. 36

4.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 37

FIGURE 23. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 37

5.0 T1/E1 APPLICATIONS .........................................................................................................................38

5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 38

5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 38

FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 38

5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 39

FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .................................................................................................... 39

5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 40

FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 40

5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 41

FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ........................................................................................................ 41

5.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 42

FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ..................................................................................... 42

5.3 LINE CARD REDUNDANCY ........................................................................................................................... 43

5.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 43

5.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 43

FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 43

5.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 44

FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 44

5.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 44

5.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 45

FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ...................................................... 45

5.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 46

FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY ........................................................ 46

5.4 POWER FAILURE PROTECTION .................................................................................................................. 47

5.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 47

5.6 NON-INTRUSIVE MONITORING .................................................................................................................... 47

FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION............................................................... 47

5.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 48

FIGURE 34. ATP TESTING BLOCK DIAGRAM ..................................................................................................................................... 48

FIGURE 35. TIMING DIAGRAM FOR ATP TESTING ........................................................................................................................... 48

5.7.1 TRANSMITTER TTIP AND TRING TESTING ............................................................................................................. 48

6.0 MICROPROCESSOR INTERFACE ......................................................................................................49

6.1 SPI SERIAL PERIPHERAL INTERFACE BLOCK ......................................................................................... 49

FIGURE 36. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 49

6.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 49

FIGURE 37. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 49

6.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 50

6.1.3 ADDR[9:0] (SCLK1 - SCLK10) ................................................................................................................................... 50

6.1.4 R/W (SCLK11)............................................................................................................................................................. 50

6.1.5 DUMMY BITS (SCLK12 - SCLK16) ............................................................................................................................ 50

6.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 50

6.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 50

FIGURE 38. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 51

6.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 52

FIGURE 39. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK .................................................................. 52

6.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 53

6.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 55

FIGURE 40. INTEL µP INTERFACE TIMING DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WHEN ALE IS NOT TIED ’HIGH’56

FIGURE 41. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS WITH ALE=HIGH ................. 57

6.5 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 58

FIGURE 42. MOTOROLA MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................... 59

FIGURE 43. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................ 60

7.0 REGISTER DESCRIPTIONS ................................................................................................................61

7.1 GLOBAL CONFIGURATION REGISTERS (0X000 - 0X00F) ......................................................................... 62

7.2 CHANNEL CONTROL REGISTERS (LINE AND SYSTEM SIDE) ................................................................. 63

7.3 OFFSET FOR PROGRAMMING THE CHANNEL NUMBER, N ..................................................................... 63

7.4 GLOBAL CONTROL REGISTERS ................................................................................................................. 64

FIGURE 44. REGISTER 0X0009H SUB REGISTERS........................................................................................................................... 69

7.5 CONTROL AND LINE SIDE DIAGNOSTIC REGISTERS .............................................................................. 74

7.6 SYSTEM SIDE DIAGNOSTIC CHANNEL CONTROL REGISTERS .............................................................. 85

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