AD7173-8BCPZ(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD7173-8BCPZ
(Rev.:Rev0)

Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC

Analog Devices 

AD7173-8

Data Sheet

Parameter

POWER DISSIPATION

Full Operating Mode

Standby Mode

Power-Down Mode

Test Conditions/Comments

Min

Unbuffered, external clock and reference;

AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V

Unbuffered, external clock and reference;

all supplies = 5 V

Unbuffered, external clock and reference;

all supplies = 5.5 V

Fully buffered, internal clock and reference

(note that REFOUT has no load); AVDD1 = 3.3 V,

AVDD2 = 2 V, IOVDD = 2 V

Fully buffered, internal clock and reference

(note that REFOUT has no load); all supplies =

5V

Fully buffered, internal clock and reference

(note that REFOUT has no load); all supplies =

5.5 V

Reference off, all supplies = 5 V

Reference on, all supplies = 5 V

Full power-down, all supplies = 5 V

Full power-down, all supplies = 5.5 V

Typ

Max

Unit

3

mW

7.35

mW

9.96

mW

10.4

mW

20.4

mW

28

mW

125

µW

2

mW

10

µW

55

µW

1 Specification is not production tested but is supported by characterization data at the initial product release.

2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale

calibration reduces the gain error to the order of the noise for the programmed output data rate.

3 This specification is noncumulative and includes MSL preconditioning effects.

4 This specification includes MSL preconditioning effects.

Rev. 0 | Page 6 of 64

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