AD7173-8BCPZ(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD7173-8BCPZ
(Rev.:Rev0)

Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AIN16 1

AIN0/REF2– 2

AIN1/REF2+ 3

AIN2 4

AIN3 5

REFOUT 6

REGCAPA 7

AVSS 8

AVDD1 9

AVDD2 10

AD7173-8

TOP VIEW

(Not to Scale)

30 AIN8

29 AIN7

28 AIN6

27 AIN5

26 AIN4

25 GPO2

24 GPIO1

23 GPIO0

22 REGCAPD

21 DGND

AD7173-8

NOTES

1. THE EXPOSED PAD SHOULD BE SOLDERED TO A SIMILAR PAD ON THE PCB

UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR

HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS

THROUGH THIS PAD ON THE PCB.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin

No. Mnemonic

Type1 Description

1 AIN16

AI

Analog Input 16. Selectable through cross point mux.

2 AIN0/REF2− AI

Analog Input 0 (AIN0)/Reference 2, Negative Input (REF2−). An external reference can be applied between

REF2+ and REF2−. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through cross

point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register.

3 AIN1/REF2+ AI

Analog Input 1 (AIN0)/Reference 2, Positive Input (REF2+). An external reference can be applied between

REF2+ and REF2−. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through cross

point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register.

4 AIN2

AI

Analog Input 2. Selectable through cross point mux.

5 AIN3

AI

Analog Input 3. Selectable through cross point mux.

6 REFOUT

AO Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.

7 REGCAPA

AO Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor.

8 AVSS

P

Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.

9 AVDD1

P

Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS.

10 AVDD2

P

Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.

11 PDSW

AO Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register.

12 XTAL1

AI

Input 1 for Crystal.

13 XTAL2/CLKIO AI/DI Input 2 for Crystal (XTAL2)/Clock Input or Output (CLKIO). See the CLOCKSEL bit settings in the ADCMODE

register (Table 25) for more information.

14 DOUT/RDY DO Serial Data Output (DOUT)/Data Ready Output (RDY). This pin serves a dual purpose. It functions as a serial

data output pin to access the output shift register of the ADC. The output shift register can contain data

from any of the on-chip data or control registers. The data-word/control word information is placed on the

DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY

output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready

pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the

pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to

a processor, indicating that valid data is available.

Rev. 0 | Page 9 of 64

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