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EVL6563H-100W 데이터 시트보기 (PDF) - STMicroelectronics

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EVL6563H-100W Datasheet PDF : 31 Pages
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AN3118
Main characteristics and circuit description
C12, R27 and R28 are connected to pin # 5 (VFF), they complete an internal peak-holding
circuit which obtains the information on the RMS mains voltage. The voltage signal at this
pin, a DC level equal to the peak voltage on pin #3 (MULT), is fed to a second input to the
multiplier for 1/V2 function necessary to compensate the control loop gain dependence on
the mains voltage. Additionally, pin #12 (RUN) is connected to pin# 5 (VFF) through the R27
and R28 resistor divider providing a voltage level for brown-out (AC mains under voltage)
protection. A voltage on the RUN pin below 0.8V shuts down (not latched) the IC and brings
its consumption to a considerably lower level. The L6563H restarts as the voltage at the pin
rises above 0.88 V.
The R21, R25, R26 and R33 dividers provide the information regarding the output voltage
level to the L6563H pin #7 (PFC_OK). It is required by the L6563H output voltage monitoring
and disable functions used for PFC protection purposes.
If the voltage on pin #7 exceeds 2.5 V the IC stops switching and restarts as the voltage on
the pin falls below 2.4 V, realizing the so called dynamic OVP, preventing the output voltage
from becoming excessive in case of transient, due to the slow response of the error
amplifier. However, if contemporaneously the voltage of the INV pin falls below 1.66 V (typ.),
a feedback failure is assumed. In this case the device is latched off. Normal operation can
be resumed only by cycling Vcc, bringing its value lower than 6 V before moving up to turn-
on threshold.
Additionally, if the voltage on pin #7 (PFC_OK) is tied below 0.23V, the L6563H is shut
down. To restart the L6563H operation the voltage on pin #7 (PFC_OK) must increase
above 0.27 V. This function can be used as a remote on/off control input.
To allow the interfacing of the board with a D2D converter the J3 connector allows the
powering of the L6563H with an external Vcc. It also gives the opportunity to manage failure
or abnormal conditions via the PWM_LATCH (#8) and PWM_STOP (#11) pins. The L6563H
operation can be also disabled or enabled to properly manage light load or failure conditions
by the D2D via the PFC_OK pin (#7), still available at pin #5 of J3 (ON/OFF). For further
details please see Section 4.6.
Doc ID 16847 Rev 2
5/31

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